LT1579CS8-3#PBF Linear Technology, LT1579CS8-3#PBF Datasheet - Page 15
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LT1579CS8-3#PBF
Manufacturer Part Number
LT1579CS8-3#PBF
Description
IC LDO REG SMART DUAL 3V 8-SOIC
Manufacturer
Linear Technology
Datasheet
1.LT1579CS-5.pdf
(20 pages)
Specifications of LT1579CS8-3#PBF
Function
Back-Up Management
Battery Type
Smart Batteries
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Example: The low-battery detector must be tripped at a
terminal voltage of 5.5V. There is a 100k pull-up resistor
to 5V on the output of the comparator and 200mV of
hysteresis is needed to prevent chatter. With a 1M resistor
for R1, what other resistor values are needed?
Using the formulas in Figure 3,
Use a standard value of 2.7M . With the 100k pull-up
resistor, this gives a sink current and logic flag voltage of
approximately 45 A at 0.4V. The hysteresis in this case
will be:
An additional 133mV of hysteresis is needed, so a resistor
and diode must be added. The value of R3 will be:
A standard value of 10M
current flowing through R3 into the comparator output is
negligible and can usually be ignored
Logic Flags
The low-battery comparator outputs and the status flags
of the LT1579 are open collector outputs capable of
sinking up to 5mA. See the curve of Logic Flag Output
Voltage vs. Current in the Typical Performance Character-
istics.
There are two status flags on the LT1579. The BACKUP
flag and the DROPOUT flag provide information on which
input is supplying power to the load and give early warning
of loss of output regulation. The BACKUP flag goes low
when the secondary input begins supplying power to the
load. The DROPOUT flag signals the dropout condition on
both inputs, warning of an impending drop in output
voltage. The conditions that set either status flag are
determined by input to output voltage differentials and
APPLICATIONS
R
Hysteresis
R
3
2
1 5
5 5
.
.
V
V
– .
18
1 5
18
1 5
.
mV
mV
U
V
V M
– .
1
133
1
0 6
INFORMATION
U
mV
V
2 7
can be used. The additional
1
.
– .
M
M
0 4
2 67
.
V
W
M
2 7
.
67
M
mV
U
10 5
.
M
current supplied to the load from each input. Normal
output deviation during transient load conditions (with
sufficient input voltages) will not set the status flags.
Timing Diagram
The timing diagram for the 5V dual battery supply is shown
in Figure 4. The schematic is the same as the 5V Dual
Battery Supply on the front of the data sheet. All logic flag
outputs have 100k pull-up resistors added. Note that there
is no time scale for the timing diagram. The timing diagram
is meant as a tool to help in understanding basic operation
of the LT1579. Actual discharge rates will be a function of
the load current and the type of batteries used. The load
current used in the example was 100mA DC.
DROPOUT
BACKUP
V
OUT
LB01
LB02
100mA
100mA
V
V
I
I
IN1
IN2
IN1
IN2
4.8V
6V
5V
6V
5V
5V
0
0
1
0
1
0
1
0
1
0
Figure 4. Basic Dual Battery Timing Diagram
A
B
C
D
LT1579
E
15
LTC1579 • F03