LTC1759CG#TR Linear Technology, LTC1759CG#TR Datasheet - Page 26
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LTC1759CG#TR
Manufacturer Part Number
LTC1759CG#TR
Description
IC CHARGER SMART BATTERY 36SSOP
Manufacturer
Linear Technology
Datasheet
1.LTC1759CGPBF.pdf
(28 pages)
Specifications of LTC1759CG#TR
Function
Charge Management
Battery Type
Smart Batteries
Voltage - Supply
11 V ~ 24 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
36-SSOP (0.200", 5.30mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
LTC1759
APPLICATIONS
below ground with the full battery potential, causing a
potential for latch-up in any of the devices connected to the
SMBus inputs. Therefore it is good design practice to
protect the SMBus inputs as shown in Figure 13.
PCB Layout Considerations
The LTC1759 has two layout critical areas. The first is the
I
circuity.
I
critical and should be kept to a minimum to reduce
parasitic capacitance. Any parasitic capacitance on this
node will cause errors in the programmed current values.
Place R
from R
DC/DC PCB Layout Hints: For maximum efficiency, the
switch node rise and fall time is kept as short as possible.
To prevent magnetic and electrical field radiation and high
frequency resonant problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power paths (primary and secondary).
1. Keep the highest frequency loop path as small and tight
26
SET
SET
as possible. This includes the bypass capacitors, with
the higher frequency capacitors being closer to the
noise source than the lower frequency capacitors. The
pin and the second is the DC/DC converter switching
Pin Layout: The LTC1759 I
SET
SET
to the LTC1759 PROG pin pad is not critical.
resistor directly next to the I
V
IN
Figure 12. V
Figure 11. V
U
V
M3
BAT
100k
D5
1N4148
CHGEN
BAT
IN
INFORMATION
SDB
U
Crowbar Protection
Crowbar Protection
M4
TPO610
INFET
LTC1759
R
SET
S4
1759 F12
W
LTC1759
pin lead length is
SET
1759 F11
V
pad. The trace
CC
U
2. Run long power traces in parallel. Best results are
3. If possible, use a ground plane under the switcher
4. Keep signal or analog ground separate. Tie this analog
5. For best current programming accuracy provide a Kelvin
Interfacing with a Selector
The LTC1759 is designed to be used with a true analog
multiplexer for the thermistor sensing path. Some selec-
tor ICs from various manufacturers may not implement
this. Consult LTC applications department for more infor-
mation.
Electronic Loads
The LTC1759 is designed to work with a real battery.
Electronic loads will create instability within the LTC1759
preventing accurate programming currents and voltages.
Consult LTC applications department for more informa-
tion.
highest frequency power path loop has the highest
layout priority. For best results, avoid using vias in this
loop and keep the entire high frequency loop on a single
external PCB layer. If you must, use multiple vias to
keep the impedance down (see Figure 15).
achieved if you run each trace on separate PCB layer
one on top of the other for maximum capacitance
coupling and common mode noise rejection.
circuitry to minimize capacitive interplane noise cou-
pling.
ground back to the power supply at the output ground
using a single point connection.
connection from R
as an example.
CONNECTOR
TO BATTERY
SENSE
V
Figure 13
DD
to R
FOR ESD PROTECTION
FOR ESD AND LATCH-UP
PROTECTION
S1
TO SYSTEM
and R
1759 F13
S2
. See Figure 14