DS2746G+T&R Maxim Integrated Products, DS2746G+T&R Datasheet - Page 14

• Manufacturer Part Number: DS2746G+T&R
• Description: IC MON BATTERY 2-WIRE 10-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of DS2746G+T&R

• Function: Fuel, Gas Gauge/Monitor
• Battery Type: Lithium-Ion (Li-Ion); Nickel-Metal Hydride (NiMH)
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS2746 Low-Cost 2-Wire Battery Monitor
Bus Idle
The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high
when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL
is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL
is high. A REPEATED START condition (Sr) can be used in place of a STOP then START sequence to terminate
one transaction and begin another without returning the bus to the idle state. In multimaster systems, a
REPEATED START allows the master to retain control of the bus. The START and STOP conditions are the only
bus activities in which the SDA transitions when SCL is high.
Acknowledge Bits
Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the
master and the DS2746 slave generate acknowledge bits. To generate an Acknowledge, the receiving device must
pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL
returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising edge of
the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits
allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is
busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should re-
attempt communication.
Data Order
A byte of data consists of 8 bits ordered most significant bit (msb) first. The least significant bit (lsb) of each byte is
followed by the Acknowledge bit. DS2746 registers composed of multibyte values are ordered most significant byte
(MSB) first. The MSB of multibyte registers is stored on even data memory addresses.
Slave Address
A bus master initiates communication with a slave device by issuing a START condition followed by a Slave
Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2746 continuously monitors for a
START condition followed by its slave address. When the DS2746 receives a slave address that matches its Slave
Address, it responds with an Acknowledge bit during the clock period following the R/W bit. The 7-bit Slave
Address is fixed.
DS2746 Slave Address
0110110
Read/Write Bit
The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0
selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a read
transaction, with the following bytes being read from the stave by the master.
Bus Timing
The DS2746 is compatible with any bus timing up to 400kHz. No special configuration is required to operate at any
speed.
2-Wire Command Protocols
The command protocols involve several transaction formats. The simplest format consists of the master writing the
START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2746. More
complex formats such as the Write Data, Read Data and Function command protocols write data, read data and
execute device specific operations. All bytes in each command format require the slave or host to return an
Acknowledge bit before continuing with the next byte. Each function command definition outlines the required
transaction format. The following key applies to the transaction formats.
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