ADP3806JRU-12.6-RL Analog Devices Inc, ADP3806JRU-12.6-RL Datasheet - Page 11

• Manufacturer Part Number: ADP3806JRU-12.6-RL
• Description: IC CHARGER LI-ION 12.6V 24-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of ADP3806JRU-12.6-RL

• Rohs Status: RoHS non-compliant
• Function: Charge Management
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 13 V ~ 20 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Other names: ADP3806JRU-12.6RL

The oscillator frequency is set by the external capacitor at the
CT pin and the internal current source of 150 mA according to
the following formula:
A 180 pF capacitor sets the frequency to 250 kHz. The frequency
can also be synchronized to an external oscillator by applying a
square wave input on SYNC. The SYNC function is designed
to allow increases only in the oscillator frequency. The f
should be no more than 20% higher than f
of the SYNC input is not important and can be anywhere
between 5% and 95%.
7 V Bootstrap Regulator
The driver stage is powered by the internal 7 V bootstrap regu-
lator, which is available at the BSTREG pin. Because the
switching currents are supplied by this regulator, decoupling
must be added. A 0.1 mF capacitor should be placed close to the
ADP3806, with the ground side connected close to the power
ground pin, PGND. This supply is not recommended for use
externally due to high switching noise.
Bootstrapped Synchronous Driver
The PWM comparator controls the state of the synchronous
driver shown in Figure 3. A high output from the PWM com-
parator forces DRVH on and DRVL off. The drivers have an on
resistance of approximately 6 W for fast rise and fall times when
driving external MOSFETs. Furthermore, the bootstrapped
drive allows an external NMOS transistor for the main switch
instead of a PMOS. An external boost diode should be con-
nected between BSTREG and BST, and a boost capacitor of
0.1 mF must be added externally between BST and SW. The
voltage between BST and SW is typically 6.5 V.
The DRVL pin switches between BSTREG and PGND. The 7 V
output of BSTREG drives the external NMOS with high VGS
to lower the on resistance. PGND should be connected close to
the source pin of the external synchronous NMOS. When DRVL
is high, this turns on the lower NMOS and pulls the SW node
to ground. At this point, the boost capacitor is charged up through
the boost diode. When the PWM switches high, DRVL is turned
off and DRVH turns on. DRVH switches between BST and
SW. When DRVH is on, the SW pin is pulled up to the input
supply (typically 16 V), and BST rises above this voltage by
approximately 6.5 V.
Overlap protection is included in the driver to ensure that both
external MOSFETs are not on at the same time. When DRVH
turns off the upper MOSFET, the SW node goes low due to the
inductor current. The ADP3806 monitors the SW voltage, and
DRVL goes high to turn on the lower MOSFET when SW goes
below 1 V. When DRVL turns off, an internal timer adds a
delay of 50 ns before turning DRVH on.
When the charge current is low, the DRVLSD comparator
signals the driver to turn off the low side MOSFET and DRVL
is held low. As shown in Figure 1, the DRVLSD comparator
looks at the output of AMP1. The DRVLSD threshold is set to
1.2 V, corresponding to 48 mV differential voltage between the
CS pins.
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SYNC
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The driver stage monitors the voltage across the BST capacitor
with CMP3. When this voltage is less than 4 V, CMP3 forces a
minimum offtime of 200 ns. This ensures that the BST capacitor is
charged even during DRVLSD. However, because a minimum
off time is only forced when needed, the maximum duty cycle is
greater than 99%.
2.5 V Precision Reference
The voltage at the BAT pin is compared to an internal preci-
sion, low temperature drift reference of 2.5 V. The reference is
available externally at the REF pin. This pin should be bypassed
with a 100 pF capacitor to the analog ground pin, AGND. The
reference can be used as a precision voltage externally. How-
ever, the current draw should not be greater than 100 mA, and
noisy, switching type loads should not be connected.
6 V Regulator
The 6 V regulator supplies power to most of the analog circuitry
on the ADP3806. This regulator should be bypassed to AGND
with a 0.1 mF capacitor. This reference has a 3 mA source capa-
bility to power external loads if needed.
LC
The ADP3806 provides a low current (LC) logic output to signal
when the current sense voltage (V
and the battery voltage is greater than 95%. LC is an open-drain
output that is pulled low when V
the low current threshold condition is reached, LC is pulled
high by an external resistor to REF or another appropriate pull-up
voltage. To determine when LC goes low, an internal compara-
tor senses when the current falls below 12.5% of full scale (20 mV
across the CS pins). The comparator has hysteresis to prevent
oscillation around the trip point.
To prevent false triggering (such as during soft-start), the com-
parator is only enabled when the battery voltage is within 5% of
its final voltage. As the battery is charging up, the comparator
will not go low even if the current falls below 12.5% as long as
the battery voltage is below 95% of full scale. Once the battery
has risen above 95%, the comparator is enabled. This pin can
be used to indicate the end of the charge process.
System Current Sense
An uncommitted differential amplifier is provided for additional
high side current sensing. This amplifier, AMP2, has a fixed
gain of 50 V/V from the SYS+ and SYS– pins to the analog
output at ISYS. ISYS has a 1 mA source capability to drive an
external load. The common-mode range of the input pins is
from 4 V to VCC. This amplifier is the only part of the ADP3806
that remains active during shutdown. The power to this block is
derived from the bias current on the SYS+ and SYS– pins.
A separate comparator at the LIMIT pin signals when the voltage
on the ISYS pin exceeds 2.5 V typically. The internal compara-
tor has an open-drain output, which produces the function
shown in the TPC 10 graph of V
pin should be externally pulled up to 5 V, 2.5 V, or some other
voltage as needed through a resistor. This graph was taken with
a 50 kW pull-up resistor to 5 V and to 2.5 V. When ISYS is
below 2.4 V, the LIMIT pin has high output impedance. The
open-drain output is capable of sinking 700 mA when the thresh-
old is exceeded. This comparator is turned off during shutdown
to conserve power.
CS
LIMIT
CS
is above the threshold. When
) is below a fixed threshold
versus V
ISYS
ADP3806
. The LIMIT