TC7117CPL Microchip Technology, TC7117CPL Datasheet - Page 10

• Manufacturer Part Number: TC7117CPL
• Description: IC ADC 3 1/2DGT LED DVR 40-DIP
• Manufacturer: Microchip Technology

Specifications of TC7117CPL

• Display Type: LED
• Configuration: 7 Segment
• Digits Or Characters: A/D 3.5 Digits
• Current - Supply: 800µA
• Voltage - Supply: 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Resolution (bits): 3.5bit
• Input Channel Type: Differential
• Data Interface: Parallel
• Supply Voltage Range - Analog: 5V
• Supply Current: 800µA
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 158-1057; 158-1057

TC7116/A/TC7117/A
FIGURE 3-5:
3.2.1
The clocking method used for the TC7116/TC7116A
and TC7117/TC7117A is shown in Figure 3-6. Three
clocking methods may be used:
1.
2.
3.
The oscillator frequency is ÷4 before it clocks the
decade counters. It is then further divided to form the
three convert cycle phases: Signal Integrate (1000
counts), Reference De-integrate (0 to 2000 counts),
and Auto-Zero (1000 to 3000 counts). For signals less
than full scale, auto-zero gets the unused portion of ref-
erence de-integrate. This makes a complete measure
cycle of 4000 (16,000 clock pulses), independent of
input voltage. For 3 readings per second, an oscillator
frequency of 48kHz would be used.
DS21457B-page 10
OSC1
An external oscillator connected to Pin 40.
A crystal between Pins 39 and 40.
An RC network using all three pins.
40
Typical Segment Output
Internal Digital Ground
SYSTEM TIMING
TC7116A
OSC2
0.5mA
2mA
Clock
TC7116
From Comparator Output
39
TC7116/TC7116A DIGITAL SECTION
Segment
Output
To Switch Drivers
V+
OSC3
38
Internal Digital Ground
Thousands
÷
4
7-Segment
Hundreds
Decode
Logic Control
To achieve maximum rejection of 60Hz pickup, the sig-
nal integrate cycle should be a multiple of 60Hz. Oscil-
lator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
48kHz, 40kHz, etc. should be selected. For 50Hz rejec-
tion, oscillator frequencies of 200kHz, 100kHz,
66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings per second) will reject both
50Hz and 60Hz.
3.2.2
When HLDR is at a logic HIGH, the latch will not be
updated. Analog-to-digital conversions will continue,
but will not be updated until HLDR is returned to LOW.
To continuously update the display, connect to TEST
(TC7116/TC7116A) or GROUND (TC7117/TC7117A),
or disconnect. This input is CMOS compatible with
70kΩ typical resistance to TEST (TC7116/TC7116A) or
GROUND (TC7117/TC7117A).
HLDR
LCD Phase Driver
1
7-Segment
Latch
Decode
Tens
HOLD READING INPUT
V
~70kΩ
TH
= 1V
7-Segment
Decode
©
Units
2002 Microchip Technology Inc.
21
÷
500Ω
6.2V
200
Backplane
35
37
26
V-
V+
TEST