TC7117CPL Microchip Technology, TC7117CPL Datasheet - Page 7

IC ADC 3 1/2DGT LED DVR 40-DIP

TC7117CPL

Manufacturer Part Number
TC7117CPL
Description
IC ADC 3 1/2DGT LED DVR 40-DIP
Manufacturer
Microchip Technology
Datasheets

Specifications of TC7117CPL

Display Type
LED
Configuration
7 Segment
Digits Or Characters
A/D 3.5 Digits
Current - Supply
800µA
Voltage - Supply
5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
40-DIP (0.600", 15.24mm)
Resolution (bits)
3.5bit
Input Channel Type
Differential
Data Interface
Parallel
Supply Voltage Range - Analog
5V
Supply Current
800µA
Digital Ic Case Style
DIP
No. Of Pins
40
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Interface
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
158-1057
158-1057

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TC7117CPL
Manufacturer:
HARRIS
Quantity:
6 218
TABLE 2-1:
3.0
(All Pin Designations Refer to 40-Pin PDIP.)
3.1
Figure 3-1 shows the block diagram of the analog sec-
tion for the TC7116/TC7116A and TC7117/TC7117A.
Each measurement cycle is divided into three phases:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), and
(3) Reference Integrate (REF), or De-integrate (DE).
3.1.1
High and low inputs are disconnected from the pins and
internally shorted to analog common. The reference
capacitor is charged to the reference voltage. A feed-
back loop is closed around the system to charge the
auto-zero capacitor (C
ages in the buffer amplifier, integrator, and comparator.
Since the comparator is included in the loop, AZ accu-
racy is limited only by system noise. The offset referred
to the input is less than 10µV.
©
(40-Pin CERDIP)
2002 Microchip Technology Inc.
(40-Pin PDIP)
Pin Number
35
36
37
38
39
40
DETAILED DESCRIPTION
Analog Section
AUTO-ZERO PHASE
PIN FUNCTION TABLE (CONTINUED)
(44-Pin PQFP)
Pin Number
AZ
) to compensate for offset volt-
43
44
3
4
6
7
Symbol
V
OSC3
OSC2
OSC1
TEST
REF
V+
+
Positive Power Supply Voltage.
The analog input required to generate a full scale output (1999 counts). Place
100mV between Pins 32 and 36 for 199.9mV full scale. Place 1V between
Pins 35 and 36 for 2V full scale. See Section 4.6, Reference Voltage.
Lamp test. When pulled HIGH (to V+), all segments will be turned on and the dis-
play should read -1888. It may also be used as a negative supply for externally
generated decimal points. See Section 3.1.7, TEST for additional information.
See Pin 40.
See Pin 40.
Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock (3 readings per
section), connect Pin 40 to the junction of a 100kΩ resistor and a 100pF capaci-
tor. The 100kΩ resistor is tied to Pin 39 and the 100pF capacitor is tied to Pin 38.
3.1.2
The auto-zero loop is opened, the internal short is
removed, and the internal high and low inputs are con-
nected to the external pins. The converter then inte-
grates the differential voltages between V
for a fixed time. This differential voltage can be within a
wide Common mode range: 1V of either supply. How-
ever, if the input signal has no return with respect to the
converter power supply, V
common to establish the correct Common mode volt-
age. At the end of this phase, the polarity of the
integrated signal is determined.
TC7116/A/TC7117/A
SIGNAL INTEGRATE PHASE
Description
IN
- can be tied to analog
DS21457B-page 7
IN
+ and V
IN
-

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