MAX6961ATH+T Maxim Integrated Products, MAX6961ATH+T Datasheet - Page 19

• Manufacturer Part Number: MAX6961ATH+T
• Description: IC DRVR LED 8X8 44-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX6961ATH+T

• Display Type: LED
• Configuration: 8 x 8 (Matrix)
• Interface: 4-Wire Serial
• Digits Or Characters: Any Digit Type
• Current - Supply: 7.5mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFN Exposed Pad
• Number Of Segments: 64
• Low Level Output Current: 750 mA
• High Level Output Current: 48 mA
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Supply Current: 9 mA
• Maximum Power Dissipation: 2162 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 19. Global Panel Configuration—Ripple Sync Control (R Data Bit D4) Format
Table 20. Global Panel Configuration—Mux Flip Control (F Data Bit D5) Format
The MAX6960s driving a display panel must be config-
ured before the panel can be used to display images.
The configuration involves the global panel configura-
tion register (Table 15–Table 22), the global driver
devices register (Table 13), and the global driver rows
register (Table 14). The global driver devices register
should be written with the total number of MAX6960s
interconnected on the 3-wire interface, minus 1 (Table
13). For the four panel examples shown in Figures 1
and 2, 24 MAX6960s are used, so the global driver
devices register should be written with the value 23, or
0x17.
The global driver rows register should be written with
the number of MAX6960s per panel row, minus 1
(Table 14). For the panel examples shown in Figure 1
and Figure 2, there are six MAX6960s per row, so the
global driver rows register should be written with the
value 5.
The values stored in the global driver devices register
and the global driver rows register, together with the C
and Pl bits in the global panel configuration register
(Tables 21 and 22), are used by the 3-wire interface
Ripple sync is disabled; all interconnected
MAX6960s on the same 4-wire bus resynchronize
together.
Ripple sync is enabled; all interconnected
MAX6960s on the same 4-wire bus resynchronize
with a 0.9537µs delay between adjacent devices.
Mux flip is disabled: all interconnected MAX6960s
on the same 3-wire bus resynchronize to the
multiplex timing shown in Figure 11.
Mux flip is enabled: all interconnected MAX6960s on
the same 3-wire bus resynchronize with MAX6960s
with even driver addresses (0, 2, 4 to 254) operating
to the multiplex timing shown in Figure 11, and
MAX6960s with odd driver addresses (1, 3, 5 to 255)
operating to the flipped multiplex timing shown in
Figure 12.
______________________________________________________________________________________
REGISTER
REGISTER
Device Configuration
8 x 8 Matrix Graphic LED Drivers
CODE (HEX)
CODE (HEX)
ADDRESS
ADDRESS
0x0D
0x0D
0x0D
0x0D
4-Wire Serially Interfaced
configuration engine to reconfigure display memory
addressing among the interconnected MAX6960s.
The global panel configuration register contains eight
device settings (Table 15 to Table 22).
Shutdown mode is exited by clearing the S bit in the
global panel configuration register (Table 16). When
the MAX6960 is in shutdown mode, LED driver outputs
ROW1–ROW8 and COL1–COL16 are tri-stated, and
multiplexing is halted. Data in the global configuration
registers remains unaltered. For minimum supply cur-
rent in shutdown mode, logic inputs should be at GND
or V+ potential. Shutdown mode is exited by setting the
S bit in the global panel configuration register.
The invert pixels (IP) bit in the global panel configura-
tion register controls whether the display memory is
used directly or inverted (Table 17).
D7
PI
PI
D7
PI
PI
Global Panel Configuration Register
D6
C
C
D6
C
C
D5
F
F
D5
0
1
REGISTER DATA
REGISTER DATA
D4
0
1
D4
R
R
Shutdown Mode (Bit D0)
DP1
DP1
D3
DP1
DP1
D3
Invert Pixels (Bit D1)
DP0
DP0
D2
DP0
DP0
D2
D1
IP
IP
D1
IP
IP
D0
D0
S
S
S
S
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