CS5463-ISZ Cirrus Logic Inc, CS5463-ISZ Datasheet
CS5463-ISZ
Specifications of CS5463-ISZ
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CS5463-ISZ Summary of contents
Page 1
... V neous power, apparent power, active power, and reactive power for single-phase 3-wire power metering applications. The CS5463 is optimized to interface to shunt re- sistors or current transformers for current measurement, and to resistive dividers or poten- tial transformers for voltage measurement. The CS5463 features a bi-directional serial inter- face for communication with a processor and a programmable energy-to-pulse output function ...
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... Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 Page 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.1 Configuration Register ( Config ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.2 Current and Voltage DC Offset Register ( I 6.1.3 Current and Voltage Gain Register ( I 6.1.4 Cycle Count Register ( Cycle Count ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.5 PulseRateE Register ( PulseRateE ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.6 Instantaneous Current, Voltage, and Power Registers ( DCoff DCoff , CS5463 DS678F2 ...
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... Trig ) . . . . . . . . . . . . . . . . . . . . . . . . . Min ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Gain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Off 2 PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2 PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS5463 ) . . . . . . . . . . . . . . . . . . 28 RMS , ACoff ACoff , AVG , peak peak ) . . . . . . . . . . . . . . . . . . . . . . ...
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... LIST OF FIGURES Figure 1. CS5463 Read and Write Timing Diagrams.................................................................. 12 Figure 2. Timing Diagram for E1 Figure 3. Data Measurement Flow Diagram. .............................................................................. 14 Figure 4. Power Calculation Flow. .............................................................................................. 15 Figure 5. Active and Reactive Energy Pulse Outputs ................................................................. 17 Figure 6. Apparent Energy Pulse Outputs .................................................................................. 18 Figure 7. Voltage Channel Sign Pulse outputs ........................................................................... 18 Figure 8. PFMON Output to Pin Figure 9 ...
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... OVERVIEW The CS5463 is a CMOS monolithic power measurement device with a computation engine and an ener- gy-to-frequency pulse output. The CS5463 combines a programmable gain amplifier, two ∆Σ Ana- log-to-Digital Converters (ADCs), system calibration, and a computation engine on a single chip. The CS5463 is designed for power measurement applications and is optimized to interface to a current sense resistor or transformer for current measurement, and to a resistive divider or potential transformer for voltage measurement ...
Page 6
... AGND – Analog ground. PFMON – The power fail monitor pin monitors the analog supply. If the analog supply does not meet or falls below PFMON’s voltage threshold, a Low-supply Detect (LSD) event is set in the status register. CS5463 Crystal In Serial Data Input Energy Output 2 ...
Page 7
... V RMS Input Range 5% - 100% (DC, 50, 60 Hz) CMRR All Gain Ranges (Gain = 10) IIN (Gain = 50) (Gain = 50) THD (50, 60 Hz) (Gain = 10) IC (Gain = 50) EII (Gain = 10 (Gain = 50) OD (Note 3) GE CS5463 Min Typ Max Unit 3.135 5.0 5.25 V 4.75 5 -40 - +85 °C Conditions. Min Typ ...
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... Hz) sinewave is imposed onto the + supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to AGND. Then the CS5463 is commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. ...
Page 9
... MAX MIN VREFO UT T AVG MAX A Recommended Operating Symbol (Note 12 and 13) (Voltage Channel, 60 Hz) DCLK = MCLK/K (Both Channels) OWR - (Note 14) FSCR Referred to Input (Note 15 XIN SCLK and RESET V IL XIN SCLK and RESET CS5463 Min Typ Max +2.4 +2.5 +2 +2.4 +2.5 +2 ...
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... Configuration Register bits PC[6:0] are set to “0000000”. 16. The MODE pin is pulled low by an internal resistor. 10 Symbol Min V IL XIN SCLK and RESET (VD+) - 1.0 out out OL (Note 16 out CS5463 Typ Max Unit - - 0. 0 0 ±1 ±10 µ ± ...
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... Any Digital Output t fall SCLK Any Digital Output t ost SCLK Pulse Width High t 1 Pulse Width Low Pulse Width Low t 9 Pulse Width High CS5463 Conditions. Min Typ Max Unit - - 1.0 µ 100 µ 1.0 µ 100 µ MHz 200 - - ns 200 - ...
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... Figure 1. CS5463 Read and Write Timing Diagrams SDI Write Timing (Not to Scale SDO Read Timing (Not to Scale Auto-boot Sequence Timing (Not to Scale CS5463 DS678F2 ...
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... OUT (Note 26 All Analog Pins V INA All Digital Pins V IND stg Min Typ Max 250 - - 244 - - 1 248 - - Min Typ Max -0.3 - +6.0 -0 ± 100 - - 500 - 0.3 - (VA+) + 0.3 -0.3 - (VD+) + 0.3 - -65 - 150 CS5463 Unit µs µs µs µs µs Unit °C °C 13 ...
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... Order SINC 3 ∆Σ PGA CURRENT Modulator 4. THEORY OF OPERATION The CS5463 is a dual-channel analog-to-digital convert- er (ADC) followed by a computation engine that per- forms power calculations and conversion. The data flow for the voltage and current channel measurement and the power calculation algo- rithms are depicted in Figure 3 and 4, respectively ...
Page 15
... Output E3 can also be set to display the sign of the voltage applied to the voltage channel or the PFMON comparator output. The apparent power (S) is the combination of the active power and reactive power, without reference to an im- pedance phase angle, and is calculated by the CS5463 using the following formula: × ...
Page 16
... Voltage Channel The output of the line voltage resistive divider or trans- former is connected to the VIN+ and VIN- input pins of the CS5463. The voltage channel is equipped with a 10x fixed-gain amplifier. The full-scale signal level that can be applied to the voltage channel is ± 250 mV. If the ...
Page 17
... Energy Pulse Output The CS5463 provides three output pins for energy reg- istration. By default, E1 registers active energy, E3 reg- isters reactive energy, and E2 indicates the sign of both active and reactive energy ...
Page 18
... Setting bits E3MODE[1: (10b) in the Operational × PulseRate Mode Register outputs the sign of the voltage channel 2 on pin E3. Figure 7 illustrates the output format with volt- age channel sign Figure 7. Voltage Channel Sign Pulse outputs CS5463 Figure 5 Figure 2 on page 13. × × × × × VIN VGAIN ...
Page 19
... Level Level Duration Figure 9. Sag and Fault Detect Min register is less than the value in the Active register. ) are constant val- off CS5463 Dura used to ) gain 19 ...
Page 20
... Fahrenheit scale. 5.9 Voltage Reference The CS5463 is specified for operation with a +2.5 V ref- erence between the VREFIN and AGND pins. To utilize the on-chip 2.5 V reference, connect the VREFOUT pin to the VREFIN pin of the device. The VREFIN can be used to connect external filtering and/or references ...
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... DCLK will equal 3 MHz, which is a valid value for DCLK. 5.13 Event Handler The INT pin is used to indicate that an internal error or event has taken place in the CS5463. Writing a logic 1 to any bit in the Mask Register allows the corresponding bit in the Status Register to activate the INT pin. The in- terrupt condition is cleared by writing a logic 1 to the bit that has been set in the Status Register ...
Page 22
... Software Register* Pages 32 Pages 0 - 0x1F 0x000 * Accessed using register read/write commands. Figure 11. CS5463 Memory Map Example: Reading register 6 in page 3. 1. Write 3 to page register with command and data: 0x7E 0x00 0x00 0x03 2. Read register 6 with command: 0x0C 0xFF 0xFF 0xFF ...
Page 23
... To conserve power the CS5463 has two power-down states. In stand-by state all circuitry, except the analog/digital clock generators, is turned off. In the sleep state all circuitry, except the command decoder, is turned off. Bringing the CS5463 out of sleep state requires more time than out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog oscillator. ...
Page 24
... Operation Mode Temperature Average Reactive Power AVG Instantaneous Reactive Power Peak Current Peak Voltage Peak Reactive Power calculated from Power Triangle Trig Power Factor Interrupt Mask Apparent Power Control Harmonic Active Power H Fundamental Active Power F Fundamental Reactive Power / Page F CS5463 th SCLK. DS678F2 ...
Page 25
... CAL4 CAL3 CAL2 CAL1 CAL0 The CS5463 can perform system calibrations. Proper input signals must be applied to the current and voltage chan- nel before performing a designated calibration. CAL[4:0]* Designates calibration to be performed 01001 = Current channel DC offset 01010 = Current channel DC gain 01101 = Current channel AC offset ...
Page 26
... DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be- tween 1 and 16. Note that a value of “0000” will set (not zero reset PC4 PC3 PC2 IMODE IINV iCPU K3 Phase Compensation CS5463 PC1 PC0 Igain page 39 for more infor- DS678F2 ...
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... When DC Offset calibration is performed, the ) DCoff , V DCoff DC Offset Calibration Sequence on page 37 for more information -16 ..... ..... -17 ..... Energy Pulse Output CS5463 ) -18 -19 -20 -21 - < 1.0, with the binary point to the right of DCoff -17 -18 -19 -20 - -18 -19 -20 -21 - page 17 for more information. ...
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... MSB. Negative values have no significance -17 ..... Active - -17 ..... < 1.0. The value is represented in two's complement Active , V ) RMS RMS ) - -18 ..... -17 ..... CS5463 -18 -19 -20 -21 - -18 -19 -20 -21 - -19 -20 -21 -22 - < 1.0, with the binary point , V RMS RMS -18 -19 -20 -21 - Perform- ε < 1.0, with the binary point to the ...
Page 29
... Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscil- DS678F2 ) off - -17 ..... CRDY EOR IFAULT VOD IOD Register overflows. RMS Register overflows. RMS overflows. ACTIVE CS5463 -18 -19 -20 -21 - register, and can be active off IOR VOR VSAG LSD FUP IC Sag and Fault Detect Feature on page Sag and Fault Detect Feature on page ...
Page 30
... Enables an extra sample of current channel delay. XVDEL and XIDEL can not be enabled at the same time ACoff ACoff - -17 ..... are initialized to zero on reset, allowing for uncalibrated normal operation. ACoff < 1.0, with the binary point to the right of the MSB , I ACoff ACoff IIR E3MODE1 CS5463 ) -18 -19 -20 -21 - E2MODE XVDEL 2 1 E3MODE0 POS AFC DS678F2 LSB - ...
Page 31
... Q averaged over N samples. The results are signed values with. The value , V peak peak - -17 ..... registers contain the instantaneous current and voltage with peak < 1.0, with the binary point to the right of the MSB peak peak CS5463 -11 -12 -13 -14 - AVG -18 -19 -20 -21 - < 1.0, with the binary point to the ...
Page 32
... Apparent power (S) is the product of the V the range of 0 ≤ S < 1.0, with the binary point to the right of the MSB Trig - -17 ..... -17 ..... -17 ..... and I , The value is represented in unsigned notation and in RMS RMS CS5463 -18 -19 -20 -21 - Power Measurements -18 -19 -20 -21 - -18 -19 -20 -21 - DS678F2 LSB -23 2 ...
Page 33
... P the MSB. DS678F2 INTOD ) -17 ..... calculated by subtracting the Fundamental Active Power from the Active -17 ..... calculated by performing a discrete Fourier transform (DFT) at the rele- F CS5463 NOCPU NOOSC -18 -19 -20 -21 - < 1.0, with H -18 -19 -20 -21 - < 1.0, with the binary point to the right STOP 0 LSB -23 ...
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... MSB. H 6.1.24 Page Register Address: 31 (write only) MSB Default = 0x00 Determines which register page the serial port will access -17 ..... calculated by performing a discrete Fourier transform (DFT) at the relevant H LSB CS5463 -18 -19 -20 -21 - DS678F2 LSB -23 2 ...
Page 35
... Min ) Gain -11 ..... utilized to convert from one temperature scale Gain C) is the default. Values will be within in the range of 0 ≤ Off - -17 ..... CS5463 -18 -19 -20 -21 - register is less than Load Active -12 -13 -14 -15 - < 128. The value Gain On-chip ...
Page 36
... Sag and Fault Detect Feature , ISAG ) Duration Duration defines the number of instanta- ) Duration Sag and Fault Detect Feature on page 19. , ISAG ) Level Level -18 -19 -20 - defines the voltage level that the magnitude < 1.0, with the binary point to the Level on page 19. CS5463 LSB LSB -22 - DS678F2 ...
Page 37
... The computational flow of the calibration sequences are illustrated in Figure 12. The flow applies to both the volt- age channel and current channel. 7.1.1 Calibration Sequence The CS5463 must be operating in its active state and ready to accept valid commands. Refer to Section 5.16 Commands on page 23. The calibration algorithms are dependent on the value N in the Cycle Count Register (see Figure 12) ...
Page 38
... The maximum value that the gain registers can attain is 4. Therefore, if the signal level of the applied input is low enough that it causes the CS5463 to attempt to set either gain register higher than 4, the gain calibration result will be invalid and all CS5463 results obtained while performing measure- ments will be invalid ...
Page 39
... AC offset register with the product. 7.2 Phase Compensation The CS5463 is equipped with phase compensation to cancel out phase shifts introduced by the measurement element. Phase Compensation is set by bits PC[6:0] in the Configuration Register and bits XVDEL and XIDEL ...
Page 40
... AUTO-BOOT MODE USING E When the CS5463 MODE pin is asserted (logic 1), the CS5463 auto-boot mode is enabled. In auto-boot mode, the CS5463 downloads the required commands and register data from an external serial E the CS5463 to begin performing energy measurements. 8.1 Auto-boot Configuration A typical auto-boot serial connection between the ...
Page 41
... CS5466 must be referenced to the line side of the power line. This means that the common-mode poten- tial of the CS5463 will track the high-voltage levels, as well as low-voltage levels, with respect to earth ground. Isolation circuitry is required when an earth-ground-ref- erenced communication interface is connected ...
Page 42
... XIN Clock Source 19 RESET SDI 6 Serial SDO Data 5 SCLK Interface 20 INT DGND 4 Mech. Counter or Stepper Motor 5 kΩ 10 kΩ 10 Ω 0.1 µ VD+ CS5463 17 PFMON 2 CPUCLK 1 XOUT 4.095 MHz Optional 24 XIN Clock Source 19 RESET Serial SDO Data 5 SCLK Interface 20 INT AGND ...
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... VA+ VD+ CS5463 17 PFMON 9 VIN+ 2 CPUCLK 1 XOUT 4.096 MHz Vdiff Optional 10 24 VIN- XIN Clock 16 Source IIN+ 19 RESET 7 Idiff CS 23 SDI 6 Interface SDO 15 5 IIN- SCLK 20 INT 12 VREFIN VREFOUT 21 E1 DGND AGND 13 4 Mech. Counter or Stepper Motor CS5463 Serial Data 43 ...
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... JEDEC #: MO-150 Controlling Dimension is Millimeters. CS5463 ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 8.20 8.50 7.80 8.20 5 ...
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... ORDERING INFORMATION Model CS5463-IS CS5463-ISZ (lead free) 12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5463-IS CS5463-ISZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS678F2 Temperature -40 to +85 °C Peak Reflow Temp MSL Rating* 240 °C 260 °C CS5463 Package 24-pin SSOP ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 46 Registers. Min www.cirrus.com CS5463 Changes DS678F2 ...