CS5460A-BSZ Cirrus Logic Inc, CS5460A-BSZ Datasheet
CS5460A-BSZ
Specifications of CS5460A-BSZ
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CS5460A-BSZ Summary of contents
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... The CS5460A has on-chip func- tionality to facilitate system-level calibration. The “Auto-boot” feature allows the CS5460A to function ‘stand-alone’ and to initialize itself on sys- tem power-up ...
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... Digital High-Pass Filters ...................................................................................... 12 2.1.5 Overall Filter Response ....................................................................................... 13 2.1.6 Gain and DC Offset Adjustment .......................................................................... 13 2.1.7 Real Energy and RMS Computations ................................................................. 13 2.2 Performing Measurements ............................................................................................... 13 2.2.1 CS5460A Linearity Performance ......................................................................... 15 2.2.2 Single Computation Cycle (C=0) ......................................................................... 15 2.2.3 Continuous Computation Cycles (C=1) ............................................................... 16 2.3 Basic Application Circuit Configurations .......................................................................... 16 3. FUNCTIONAL DESCRIPTION ............................................................................................... 21 3 ...
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... Register Write ..................................................................................................... 42 4.3.2 Register Read ..................................................................................................... 42 4.4 System Initialization ......................................................................................................... 42 4.5 Serial Port Initialization .................................................................................................... 43 4.6 CS5460A Power States ................................................................................................... 43 5. REGISTER DESCRIPTION ................................................................................................... 44 5.1 Configuration Register ...................................................................................................... 44 5.2 Current Channel DC Offset Register and Voltage Channel DC Offset Register .............. 46 5.3 Current Channel Gain Register and Voltage Channel Gain Register............................... 46 5 ...
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... LIST OF FIGURES Figure 1. CS5460A Read and Write Timing Diagrams.................................................................. 10 Figure 2. CS5460A Auto-Boot Sequence Timing.......................................................................... 11 Figure 3. Data Flow. ...................................................................................................................... 13 Figure 4. Voltage Input Filter Characteristics ................................................................................ 14 Figure 5. Current Input Filter Characteristics ................................................................................ 14 Figure 6. Typical Connection Diagram (One-Phase 2-Wire, Direct Connect to Power Line) ........ 17 Figure 7. Typical Connection Diagram (One-Phase 2-Wire, Isolated from Power Line) ............... 18 Figure 8 ...
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... Hz) (Gain = 10 (Gain = 50) (Note 6) (Gain = 10) Z inI (Gain = 50) Z inI (Gain = 10) (Gain = 50) (Note 1) VOS I (Note 1) FSE I {( VIN+ VIN- IN THD V VA- (50, 60 Hz) C inV (Note 6) Z inV (Note 1) VOS V (Note 1) FSE V CS5460A Typ Max Unit nV/° 500 mV P 100 -115 ...
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... Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. Then the CS5460A is commanded to ’continuous computation cycles’ data acquisition mode, and digital output data is collected for the channel under test ...
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... MAX MIN VREFOUT AVG MAX MIN A A Symbol V IH XIN (VD+) - 0.5 SCLK and RESET V IL XIN SCLK and RESET (VD+) - 1.0 out out OL (Note 14 out CS5460A Min Typ Max Unit +2 ppm/° +2.4 +2 Min Typ Max 0.6 VD 0.8 VD 0.8 ...
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... out OL (Note 14 out Symbol (Notes 18 and 19) Positive Digital VD+ Positive Analog VA+ Negative Analog VA OUT (Note 23 All Analog Pins V (VA-) - 0.3 INA All Digital Pins V DGND - 0.3 IND stg CS5460A Min Typ Max Unit - - 0. 0 0 ±1 ±10 µ ±10 µA ...
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... Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. DS487F4 Symbol MCLK (Note 25) SCLK Any Digital Output SCLK Any Digital Output XTAL = 4.096 MHz (Note 27) SCLK Pulse Width High Pulse Width Low Pulse Width High Pulse Width Low CS5460A Min Typ Max 2.5 4.096 1.0 ...
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... Figure 1. CS5460A Read and Write Timing Diagrams 10 CS5460A DS487F4 ...
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... DS487F4 CS5460A 11 ...
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... OVERVIEW The CS5460A is a CMOS monolithic power mea- surement device with a real power/energy compu- tation engine. The CS5460A combines two programmable gain amplifiers, two ∆Σ modulators, two high rate filters, system calibration, and rms/power calculation functions to provide instan- taneous voltage/current/power data samples as ...
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... Overall Filter Response When the CS5460A is driven with a 4.096 MHz clock (K = 1), the composite magnitude response (over frequency) of the voltage channel’s input fil- ter network is shown in Figure 4, while the com- ...
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... A register value of 1 represents the maximum possible value. Note that a value of 1.0 is never actually obtained in the registers of the CS5460A illustration, in any of the signed output registers, the maximum register value is [(2^ (2^23)] = 0.999999880791. After each A/D conversion, the CRDY bit will be asserted in ...
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... Vrms, Irms and Energy Registers are guaranteed to be within reading after the completion of each successive computation cycle. Note that until the CS5460A is calibrated (see Calibration) the accuracy of the CS5460A with respect to a reference line-voltage and line-current level on the power mains is not guaranteed to within 0 ...
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... Basic Application Circuit Configurations Figure 6 shows the CS5460A connected to a ser- vice to measure power in a single-phase 2-wire system operating from a single power supply. Note that in this diagram the shunt resistor used to mon- itor the line current is connected on the “ ...
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... In many 3-wire residential power systems within the United States, only the two Line terminals are available (neutral is not available). Figure 9 shows how the CS5460A can be configured to meter a 3-wire system when no neutral is available. Ω 500 Ω ...
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... R Burden 1k Ω Current * 0.1 µF * Refer to Input Protection ** Refer to Input Filtering CS5460A 5 k Ω Ω 10 Ω 0.1 µ VA+ VD+ CS5460A 17 PFMON VIN+ 2 CPUCLK 1 2.5 MHz to XOUT 20 MHz Optional 24 VIN- XIN Clock Source 19 IIN- RESET 7 CS Serial 23 NOTE: Current channel SDI input measures voltage Data (just like voltage input) ...
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... Burden Idiff Ω 0.1 µF * Refer to Input Protection ** Refer to Input Filtering CS5460A 5 kΩ 10 kΩ 10 Ω 0.1 µ VA+ VD+ CS5460A 17 PFMON 9 VIN+ 2 CPUCLK 1 2.5 MHz to XOUT 20 MHz Optional 24 VIN- XIN Clock Source IIN+ 19 RESET NOTE: Current channel 7 input measures voltage CS (just like voltage input) ...
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... R Burden Idiff 1k Ω 0.1 µF * Refer to Input Protection ** Refer to Input Filtering CS5460A 5 kΩ 10 kΩ 10 Ω 0.1 µ VA+ VD+ CS5460A 17 PFMON 9 VIN+ 2 CPUCLK 1 2.5 MHz to XOUT 20 MHz Vdiff Optional 10 24 VIN- XIN Clock 16 Source IIN+ 19 RESET NOTE: Current channel ...
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... K and K , such that there will be ac ceptable voltage levels on the CS5460A inputs when the power line voltage and current levels are at the maximum values of 250 V and are needed to determine the appropriate ratios I ...
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... Hz [(MCLK/K) / 1024]. A running total of the energy accumulation is maintained in an internal register (not accessible to the user) inside the CS5460A. If the amount of energy that has accumulated in this register over the most recent A/D sampling period is equal to or greater than the amount of energy that is repre- ...
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... EOUT ... EDIR Figure 11. Mechanical Counter Format on EOUT and EDIR sented by one pulse, the CS5460A will issue a “burst” of one or more pulses on EOUT (and also possibly on EDIR). The CS5460A will issue as many pulses as are necessary to reduce the run- ning energy accumulation value in this register to a value that is less than the energy represented in one pulse ...
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... Figure 12. Stepper Motor Format on EOUT and EDIR 3.3 Auto-boot Mode Using EEPROM The CS5460A has a MODE pin. When the MODE pin is set to logic low, the CS5460A is in normal op- erating mode, called host mode. This mode de- notes the normal operation of the part, that has been described so far ...
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... CS5460A has been powered on), then changing the RESET pin from active state to inactive state (low to high) will cause the CS5460A to drive the CS pin low, and af- ter this, to issue the standard EEPROM block-read command on the CS5460A’s SDO line. Once these ...
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... Interrupt and Watchdog Timer 3.4.1 Interrupt The INT pin is used to indicate that an event has taken place in the CS5460A that (may) need atten- tion. These events inform the meter system about operation conditions and internal error conditions. The INT signal is created by combining the Status Register with the Mask Register ...
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... CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. The CS5460A can be driven by a clock ranging from 2 MHz. The K divider must be set to the appropriate value such that MCLK/K will be be- tween 2.5 MHz and 5 MHz. The K divider value is set with the K[3:0] bits in the Configuration Regis- ter ...
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... These registers are up- dated by the CS5460A after either gain calibration sequence has been executed. Voltage Channel AC Offset Register and Cur- rent Channel AC Offset Register - Store additive ...
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... The calibration sequences will not run if the CS5460A is running in either of the two avail- able acquisition modes. 3.8.4 Calibration Signal Input Level For both the voltage and current channels, the dif- ...
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... External Connections + AIN XGAIN - AIN Figure 17. System Calibration of Offset. 3.8.7 Description of Calibration Algo- rithms The computational flow of the CS5460A’s AC and DC gain/offset calibration sequences are illustrat Figure 18. This figure applies to both the volt- age channel and the current channel. The I egisters + + ...
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... The value of the Cycle Count Register (N) deter- Register Values mines the number of conversions that will be per- -0.84853 -0.92231 formed by the CS5460A during a given calibration sequence. For DC offset/gain calibrations, the cal- ibration sequence always takes at least conversion cycles to complete. For AC offset/gain calibrations, the calibration sequence takes at least A/D conversion cycles to complete, (about 6 computation cycles) ...
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... CS5460A is running in ‘continuous computation cycles’ data acquisition mode. For example, the CS5460A can be set up to perform continuous computations on a purely resistive load (no induc- tance or capacitance). The PC[6:0] bits can then be adjusted until the Energy Register value is max- imized ...
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... If a voltage is presented to any of these pins that is larger than approximately 7 V (with respect to VA- pin) these protection diodes will turn on in- side the CS5460A. But in order to prevent exces- sive current levels from flowing through the device, the value of R must be large enough that when a ...
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... In this situation, the real (true) power/energy measure- ments reported by the CS5460A can contain signif- icant error, because the power factor of the sensed voltage and current signals will be significantly dif- ferent than the actual power factor of the power line voltage/current waveforms ...
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... R and C values for the volt- age/current anti-aliasing filters alternative to addition to the fine adjustment of the R and C values of the two anti-alias filters, the CS5460A’s phase compensation bits (see Phase Compensa- tion) can also be adjusted, in order to more closely match the overall time-constants of the volt- age/current input networks ...
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... The total difference between the delay on the voltage-sense fundamental and the current-sense fundamental will therefore be ~0.286 degrees. But if the phase compensation bits are set to 1111111, the CS5460A will delay the can be set to I- voltage channel signal by an additional -0.04 de- grees, which is equivalent to shifting the voltage signal forward by 0 ...
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... In these situations, the input protection resistors and corresponding input filter capacitors (discussed in the previous sections) may not be sufficient to protect the CS5460A from such high-frequency voltage/current surges. The surges may still be strong enough to cause perma- nent damage to the CS5460A. Because of this, the ...
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... CS5460A’s immunity to RFI. The exact configuration that works best can vary signif- icantly, according to the exact PCB layout/orienta- tion. Finally, note that inside the CS5460A, the Vin+, Vin-, Iin+, and Iin- pins have all been buffered with ~ internal capacitance (to VA-) in at- tempt to improve the device’ ...
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... If the device is powered-down into either stand-by or sleep power saving mode (See 4.1.5), this command will pow- er-up the device. After the CS5460A is initially powered-on, no conversions/computations will be running. If the de- vice is already powered on and the device is running either ‘single computation cycle’ or ‘continuous computation cycles’ ...
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... In the sleep state, all circuitry except the digital clock generator and the instruction decoder is turned off. Waking up the CS5460A out of sleep state requires more time than waking the device out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog clock signal. ...
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... RMS Voltage Register (computed over latest computation cycle). RMS Timebase Calibration Register. Power Offset Register. Status Register. Current Channel AC Offset Register. Voltage Channel AC Offset Register. ACoff Reserved † Reserved † Reserved † Reserved † Mask Register. Reserved † Control Register. Reserved † Reserved † CS5460A RA1 RA0 0 41 ...
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... For instance, to write the Configuration Register, the command (0x40) is transmitted to initiate a write to the Con- figuration Register. The CS5460A will acquire the serial data input from the SDI pin after 24 pulses on the SCLK pin. Once the data is received, the ...
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... Performing any of the following actions will insure that the CS5460A is operating in the active state: 0x000001 1) Power on the CS5460A. (Or if the device is al- 0x000000 ready powered on, recycle the power.) 0x400000 2) Hardware Reset ...
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... High-pass filter enabled 44 DC Offset Register (1 × 24) AC/DC Gain Register (1 × 24) DC Offset Register (1 × 24) AC/DC Gain Register (1 × 24) Cycle-Counter Registe r (1 × 24) Status Register (1 × 24) Control Register (1 x 24) Mask Register (1 × 24) Figure 21. CS5460A Register Diagram PC4 PC3 PC2 Res SI1 SI0 5 4 ...
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... Hz). If (MCLK / K) is not 4.096 MHz, the values for the range and step size should be scaled by the factor 4.096 MHz / (MCLK / K). Default setting is 0000000 = 0.0215 degrees phase delay (when MCLK = 4.096 MHz). DS487F4 CS5460A 45 ...
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... K) / (1024 ∗ N) where MCLK is master clock input frequency (into XIN / XOUT pins the clock di- vider value (as specified in the Configuration Register), and N is Cycle Count Register value -17 ..... -16 ..... ..... CS5460A -18 -19 -20 -21 - -17 -18 -19 -20 - ...
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... The value is in the range 0.0 ≤ TBC < 2.0. DS487F4 ..... -17 ..... -18 ..... < 1.0. The value is represented in binary notation, with the binary point place to are output result registers which contain unsigned values. RMS - -17 ..... CS5460A -18 -19 -20 - -19 -20 -21 - and V . The results are in RMS RMS -18 -19 -20 - LSB -4 ...
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... First, the ground-level input should be applied to the inputs. Then the AC Offset Calibration Command is should be sent to the CS5460A. After ~(6N + 30) A/D conversion cycles (where N is the value of the Cy- cle-Count Register), the gain register(s) is loaded with the square of the system AC offset value. DRDY will be asserted at the end of the calibration ...
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... Instantaneous Current Register. MATH General computation Indicates that a divide operation overflowed. This can happen normally in the course of computation. If this bit is asserted but no other bits are asserted, then there is no error, and this bit should be ignored. DS487F4 CS5460A 49 ...
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... CPUCLK output to a one-bit output port. Reduces power consumption. NOOSC 1 = saves power by disabling the crystal oscillator for external drive. STEP 1 = enables stepper-motor signals on the EOUT/EDIR pins Res Res Res Res Res Res Res INTL SYNC CS5460A Res Res Res Res Res STOP NOCPU NOOSC STEP DS487F4 ...
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... CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO pin to a high impedance state. CS should be changed when SCLK is low. MODE - When at logic high, the CS5460A can perform the auto-boot sequence with the aid of an external serial EEPROM to receive commands and settings. When at logic low, the CS5460A assumes normal “ ...
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... PFMON voltage increases ~100 mV (typical) above the PMLO voltage. Therefore, there is hysteresis in the PFMON function. Reset - When reset is taken low, all internal registers are set to their default states connection. Pin should be left floating. CS5460A DS487F4 ...
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... JEDEC #: MO-150 Controlling Dimension is Millimeters. CS5460A 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 8.20 8.50 7.80 8.20 5 ...
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... ORDERING INFORMATION CS5460A-BS 24-pin SSOP CS5460A-BSZ 24-pin SSOP 9. REVISION HISTORY Revision Date F2 September 2004 F3 August 2005 F4 November 2007 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (" ...