ADE7758ARW Analog Devices Inc, ADE7758ARW Datasheet - Page 19

• Manufacturer Part Number: ADE7758ARW
• Description: IC ENERGY METERING 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7758ARW

• Rohs Status: RoHS non-compliant
• Input Impedance: 380 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 8mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• Lead Free Status / RoHS Status: Not Compliant

Bit 7 of the gain register is used to enable the digital integrator
in the current signal path. Setting this bit activates the digital
integrator (see the DI/DT Current Sensor and Digital Integrator
section).
CURRENT CHANNEL ADC
Figure 41 shows the ADC and signal processing path for the
input IA of the current channels (same for IB and IC). In
waveform sampling mode, the ADC outputs are signed twos
complement 24-bit data-words at a maximum of 26.0 kSPS
(thousand samples per second). With the specified full-scale
analog input signal of ±0.5 V, the ADC produces its maximum
output code value (see Figure 41). This diagram shows a full-
scale voltage signal being applied to the differential inputs IAP
and IAN. The ADC output swings between 0xD7AE14
(−2,642,412) and 0x2851EC (+2,642,412).
Current Waveform Gain Registers
There is a multiplier in the signal path in the current channel
for each phase. The current waveform can be changed by ±50%
by writing a twos complement number to the 12-bit signed
current waveform gain registers (AIGAIN[11:0], BIGAIN[11:0],
and CIGAIN[11:0]). For example, if 0x7FF is written to those
registers, the ADC output is scaled up by +50%. To scale the
input by –50%, write 0x800 to the registers. Equation 2
describes mathematically the function of the current waveform
gain registers.
Changing the content of AIGAIN[11:0], BIGAIN[11:0], or
CIGAIN[11:0] affects all calculations based on its current; that
is, it affects the phase’s active/reactive/apparent energy as well as
Current
ADC
Output
Waveform
×
0.5V/GAIN
0.25V/GAIN
0.125V/GAIN
1
WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS
ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE
INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED,
THE OUTPUT WILL NOT BE FURTHER ATTENUATED.
⎛
⎜ ⎜
⎝
1
+
=
V
Content
IN
0V
V
IAP
IAN
IN
ANALOG
INPUT
RANGE
of
PGA1
GAIN[1:0]
×1, ×2, ×4
Current
2
12
GAIN[4:3]
2.42V, 1.21V, 0.6V
REFERENCE
Gain
ADC
Re
0xD7AE14
0x2851EC
AIGAIN[11:0]
0x000000
Figure 41. Current Channel Signal Path
gister
⎞
⎟ ⎟
⎠
Rev. D | Page 19 of 72
CHANNEL 1
(CURRENT WAVEFORM)
DATA RANGE
ADC OUTPUT
WORD RANGE
(2)
HPF
INTEGRATOR
DIGITAL
GAIN[7]
its current rms calculation. In addition, waveform samples are
also scaled accordingly. IGAIN should not be used when using
Mode 0 of CONSEL, COMPMODE[1:0].
Current Channel Sampling
The waveform samples of the current channel can be routed to
the WFORM register at fixed sampling rates by setting the
WAVSEL[2:0] bit in the WAVMODE register to 000 (binary)
(see Table 20). The phase in which the samples are routed is set
by setting the PHSEL[1:0] bits in the WAVMODE register.
Energy calculation remains uninterrupted during waveform
sampling.
When in waveform sample mode, one of four output sample
rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE
register (DTRT[1:0]). The output sample rate can be 26.04 kSPS,
13.02 kSPS, 6.51 kSPS, or 3.25 kSPS. By setting the WFSM bit in
the interrupt mask register to Logic 1, the interrupt request
output IRQ goes active low when a sample is available. The
timing is shown in
transferred from the ADE7758 one byte (8-bits) at a time, with
the most significant byte shifted out first.
The interrupt request output IRQ stays low until the interrupt
routine reads the reset status register (see the
DOUT
SCLK
IRQ
DIN
1
0xCB2E48
0x2BE893
0xD4176D
0x34D1B8
0x000000
0x000000
Figure 40. Current Channel Waveform Sampling
60Hz
50Hz
CURRENT RMS (IRMS)
CALCULATION
WAVEFORM SAMPLE
REGISTER
ACTIVE AND REACTIVE
POWER CALCULATION
READ FROM WAVEFORM
0
CHANNEL 1 (CURRENT WAVEFORM)
DATA RANGE AFTER INTEGRATOR
(60Hz AND AIGAIN[11:0] = 0x000)
Figure 40
CHANNEL 1 (CURRENT WAVEFORM)
DATA RANGE AFTER INTEGRATOR
(50Hz AND AIGAIN[11:0] = 0x000)
0x12
. The 24-bit waveform samples are
CURRENT CHANNE L DATA–24 BITS
SGN
Interrupts
ADE7758
section).