LTC4252A-2IMS Linear Technology, LTC4252A-2IMS Datasheet - Page 16

• Manufacturer Part Number: LTC4252A-2IMS
• Description: IC CTRLR HOTSWAP NEG VOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-2IMS

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Family Name: LTC4252A-2
• Package Type: MSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load.
However, it will not reset the circuit breaker TIMER,
PWRGD flag or shutdown cooling timer. Returning the
supply voltage to an acceptable range restarts the GATE
pin if all the interlock conditions except TIMER are met.
Only during the initial timing cycle does an OV condition
reset the TIMER.
DRAIN
Connecting an external resistor, R
DRAIN pin allows V
by large voltage transients. Below 5V, negligible pin leak-
age allows a DRAIN low comparator to detect V
than 2.385V (V
GATE low comparator, sets the PWRGD flag.
If V
V
This current is scaled up 8 times during a circuit breaker
fault and is added to the nominal 230µA TIMER current.
This accelerates the fault TIMER pull-up when the MOSFET’s
drain-source voltage exceeds V
ens the MOSFET heating duration.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor C
TIMER to provide timing for the LTC4252. Four different
charging and discharging modes are available at TIMER:
1) A 5.8µA slow charge; initial timing and shutdown
cooling delay.
2) A (230µA + 8 • I
3) A 5.8µA slow discharge; circuit breaker "cool off" and
shutdown cooling.
16
DRNCL
I
DRN
OUT
and the current flowing in R
≈
> V
V
OUT
DRNCL
DRNL
−
R
, the DRAIN pin is clamped at about
D
V
DRN
OUT
U
DRNCL
). This condition, together with the
) fast charge; circuit breaker delay.
sensing* without it being damaged
U
DRNCL
D
W
, to the dual function
D
and effectively short-
is given by:
T
U
is used at
OUT
less
(1)
4) Low impedance switch; resets the TIMER capacitor
after an initial timing delay, in UVLO, in UV and in OV
during initial timing.
For initial start-up, the 5.8µA pull-up is used. The low
impedance switch is turned off and the 5.8µA current
source is enabled when the interlock conditions are met.
C
When C
turns on and discharges C
and both SS and GATE are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than a 50mV drop across
R
C
latches off while the LTC4252-2 starts a shutdown cooling
cycle. The LTC4252-1 remains latched off until the UV pin
is momentarily pulsed low or TIMER is momentarily
discharged low by an external switch or V
UVLO and is then restored. The circuit breaker timeout
period is given by:
If V
pin leakage current, making I
V
charging of C
Intermittent overloads may exceed the 50mV threshold at
SENSE, but, if their duration is sufficiently short, TIMER
will not reach 4V and the LTC4252 will not shut the external
MOSFET off. To handle this situation, the TIMER dis-
charges C
SENSE voltage is less than 50mV. Therefore, any intermit-
tent overload with V
*V
T
T
OUT
S
OUT
, the TIMER pin charges C
charges to 4V, the GATE pin pulls low and the LTC4252-1
charges to 4V in a time period given by:
t
t
OUT
as viewed by the MOSFET; i.e., V
=
=
> V
4
230
< 5V, an internal PMOS device isolates any DRAIN
5 8
T
V C
.
DRNCL
reaches 4V (V
T
•
µ +
µ
4
slowly with a 5.8µA pull-down whenever the
A
A
V C
T
T
•
accelerates by 8 • I
during the circuit breaker fault period, the
8
T
•
I
DRN
OUT
DS
TMRH
> 5V and an aggregate duty cycle
.
T
. A GATE start-up cycle begins
), the low impedance switch
DRN
T
with (230µA + 8 • I
= 0µA in Equation (3). If
DRN
of Equation (1).
IN
dips below
DRN
425212fb
). If
(2)
(3)