LTC4261IUFD#PBF Linear Technology, LTC4261IUFD#PBF Datasheet - Page 17

• Manufacturer Part Number: LTC4261IUFD#PBF
• Description: IC CTRLR HOTSWAP W/ADC 24-QFN
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4261IUFD#PBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 9 V ~ 11.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-WFQFN Exposed Pad
• Family Name: LTC4261
• Package Type: QFN EP
• Operating Supply Voltage (min): -12V
• Operating Supply Voltage (max): -100V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
In the case of a low impedance short circuit on the load
side or an input step during battery replacement, cur-
rent overshoot is inevitable. A fast SENSE comparator
with a threshold of 150mV detects the overshoot and
immediately pulls GATE low with a 110mA current. Once
the SENSE voltage drops to 50mV, the current limit loop
takes over and servos the current as previously de-
scribed. If the short-circuit condition lasts longer than
530µs, the FET is shut down and the overcurrent fault is
registered.
In the case of an input step, after an internal clamp pulls the
RAMP pin down to 1.1V, the inrush control circuit takes
over and the current limit loop is disengaged before the
circuit breaker timer expires. From this point on, the device
works as in the initial start-up: V
rate set by I
power good signals on the PG and PGIO pins, the TMR
pin, and the SS pin are not interrupted through the input
step sequence. The waveform in Figure 6 shows how the
LTC4261/LTC4261-2 responds to an input step.
Note that the current limit threshold should be set
suffi ciently high to accommodate the sum of the load
SENSE
GATE
V
PGIO
TMR
OUT
PG
SS
RAMP
530µs
50mV
and C
R
followed by GATE pull-up. The
OC COOLING DELAY
OUT
4x
is ramped down at the
Figure 5. Overcurrent Fault and Auto-Retry
current and the inrush current to avoid engagement of
the current limit loop in the event of an input step. The
maximum value of the inrush current is given by:
where the 0.8 factor is used as a worst case margin com-
bined with the minumum threshold (45mV).
The active current limit circuit is compensated using the
capacitor C
between GATE and V
gested value for C
most pass transistors (Q1).
Overvoltage Fault
An overvoltage fault occurs when the OV pin rises above
its 1.77V threshold. This shuts off the pass transistor
immediately, sets the overvoltage present bit A0 and
the overvoltage fault bit B0, and pulls the SS pin down.
Note that the power good signals are not affected by the
overvoltage fault. If the OV pin subsequently falls back
below the threshold, the pass transistor will be allowed
I
INRUSH
INRUSH
V
Z
≤ 0 8
G
– 1.2V
with a series resistor R
. •
1.77V
LTC4261/LTC4261-2
45
G
R
is 50nF. This value should work for
mV
EE
S
, as shown in Figure 1. The sug-
2x
–
PWRGD1
DELAY
I
LOAD
2x
G
PWRGD2
DELAY
(10Ω) connected
42612 F05
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