LTC4261IUFD#PBF Linear Technology, LTC4261IUFD#PBF Datasheet - Page 26

• Manufacturer Part Number: LTC4261IUFD#PBF
• Description: IC CTRLR HOTSWAP W/ADC 24-QFN
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4261IUFD#PBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 9 V ~ 11.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-WFQFN Exposed Pad
• Family Name: LTC4261
• Package Type: QFN EP
• Operating Supply Voltage (min): -12V
• Operating Supply Voltage (max): -100V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC4261/LTC4261-2
APPLICATIONS INFORMATION
(DMY) to measure the internal clock cycle (i.e., the serial
data rate). Following the DMY bit are two channel code bits
CH1 and CH0 labeling the ADC channel (see Table 10). Ten
data bits of the ADC channel (ADC9-0) and three FAULT
register bits (B2, B1 and B0) are then sent out. A parity bit
(PRTY) ends each data stream. After that the SDAO line
enters the idle mode with SDAO pulled high.
The following data reception procedure is recommended:
0. Wait for INTV
1. Wait for SDAO falling edge.
2. The fi rst falling edge could be a glitch, so check again
3. Use the following low-to-high and high-to-low transis-
4. Wait for the second low-to-high transistion (middle of
5. Wait 3/4 of a clock cycle.
6. Sample bit CH1, wait for transistion.
26
after a delay of 10µs. If back to high, wait again. If still
low, it is the START bit.
tions to measure 1/2 of the internal clock cycle.
DMY bit).
CC
rising edge.
7. Wait 3/4 of a clock cycle.
8. Sample bit CH0, wait for transistion.
9. Wait 3/4 of a clock cycle.
10. Sample ADC9, wait for transistion.
11. Continue until all bits are read.
The above procedure can be ported to a microcontroller
or used to design a state machine in FPGA. Code should
have timeouts in case an edge is missed. Abort the read
if it takes more than double the typical time (1.2ms) for
all 18 bits to be clocked out.
A typical application circuit with the LTC4261/LTC4261-2
in the broadcast mode is illustrated in Figure 17, where
input voltage, V
Register Addresses and Contents
The register addresses and contents are summerized in
Table 1 and Table 2. The function of each register bit is
detailed in Tables 3 to 9.
DS
of the FET and V
SENSE
are monitored.
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