MIC2591B-2BTQ TR Micrel Inc, MIC2591B-2BTQ TR Datasheet - Page 25
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MIC2591B-2BTQ TR
Manufacturer Part Number
MIC2591B-2BTQ TR
Description
IC PCI HOT PLUG CTLR DUAL 48TQFP
Manufacturer
Micrel Inc
Type
Hot-Swap Controllerr
Datasheet
1.MIC2591B-2YTQ.pdf
(34 pages)
Specifications of MIC2591B-2BTQ TR
Applications
General Purpose, PCI Express
Internal Switch(s)
No
Voltage - Supply
3.3V, 12V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
MIC2591B-2BTQTR
MIC2591B-2BTQTR
MIC2591B-2BTQTR
Control Register, Slot A (CNTRLA)
8-Bits, Read/Write
The power-up default value is 00
Notes:
1.
2.
March 2005
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
MAINAPG
MAINAPG
MAINAPG
MAINAPG
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
ENABLE
ENABLE
ENABLE
ENABLE
VAUXA
VAUXA
VAUXA
VAUXA
MAINA
MAINA
MAINA
MAINA
The state of the /PWRGDA pin is the logical AND of the values of the AUXAPG and the MAINAPG bits, except when /FORCE_ONA is asserted. If
/FORCE_ONA is asserted (the pin is pulled low), and /FORCE_AENABLE is set to a logic zero, the /PWRGDA pin will be unconditionally forced to
its open-drain (“Power Not Good”) state.
The values of the MAINAPG and AUXAPG register bits are not affected by /FORCE_ONA, but will instead continue to read as high if power is
“Good,” and as low if the conditions which indicate that power is good are not met.
Bit(s)
Bit(s)
Bit(s)
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[5]
D[5]
D[5]
D[5]
D[4]
D[4]
D[4]
D[4]
D[3]
D[3]
D[3]
D[3]
Power-Up Default Value:
Read Command_Byte Value (R/W):
AUX output power-good status, Slot A
AUX output power-good status, Slot A
AUX output power-good status, Slot A
MAIN output power-good status, Slot A
MAIN output power-good status, Slot A
MAIN output power-good status, Slot A
MAIN output power-good status, Slot A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Allows or inhibits the operation of the /FORCE_ONA
Allows or inhibits the operation of the /FORCE_ONA
Allows or inhibits the operation of the /FORCE_ONA
Allows or inhibits the operation of the /FORCE_ONA
input pin
input pin
input pin
input pin
MAIN enable control, Slot A
MAIN enable control, Slot A
MAIN enable control, Slot A
MAIN enable control, Slot A
VAUX enable control, Slot A
VAUX enable control, Slot A
VAUX enable control, Slot A
VAUX enable control, Slot A
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
h
. Slot is disabled upon power-up, i.e., all supply outputs are off.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
read only
read only
read only
read only
read only
read only
read only
read only
read only
thresholds)
thresholds)
thresholds)
Function
Function
Function
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
Control Register, Slot A (CNTRLA)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
read only
read only
read only
read only
read only
read only
read only
read only
read only
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
0000 0000
0000 0010
25
b
b
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
= 00
= 02
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
h
h
1 = Power-is-Good
1 = Power-is-Good
1 = Power-is-Good
(VAUXA Output is above its UVLO
(VAUXA Output is above its UVLO
(VAUXA Output is above its UVLO
(VAUXA Output is above its UVLO
threshold)
threshold)
threshold)
threshold)
1 = Power-is-Good
1 = Power-is-Good
1 = Power-is-Good
1 = Power-is-Good
(MAINA Outputs are above their UVLO
(MAINA Outputs are above their UVLO
(MAINA Outputs are above their UVLO
(MAINA Outputs are above their UVLO
(MAINA Outputs are above their UVLO
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
0 = /FORCE_ONA is enabled
0 = /FORCE_ONA is enabled
0 = /FORCE_ONA is enabled
0 = /FORCE_ONA is enabled
1 = /FORCE_ONA is disabled
1 = /FORCE_ONA is disabled
1 = /FORCE_ONA is disabled
1 = /FORCE_ONA is disabled
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
Operation
Operation
Operation
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
M9999-033105
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]