DS1873T+ Maxim Integrated Products, DS1873T+ Datasheet - Page 26

• Manufacturer Part Number: DS1873T+
• Description: IC CTLR SFP+ ANLG LDD 28-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controllerr

Specifications of DS1873T+

• Number Of Channels: 1
• Voltage - Supply: 2.85 V ~ 3.9 V
• Current - Supply: 2.5mA
• Operating Temperature: -40°C ~ 95°C
• Package / Case: 28-WFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1873T+000

SFP+ Controller with Analog LDD Interface
26
byte (R/W = 0) and the first memory address of the
next memory row before continuing to write data.
Acknowledge polling: Any time a EEPROM page is
written, the DS1873 requires the EEPROM write time
(t
the page to EEPROM. During the EEPROM write
time, the DS1873 will not acknowledge its slave
address because it is busy. It is possible to take
advantage of that phenomenon by repeatedly
addressing the DS1873, which allows the next page
to be written as soon as the DS1873 is ready to
receive the data. The alternative to acknowledge
polling is to wait for maximum period of t
before attempting to write again to the DS1873.
EEPROM write cycles: When EEPROM writes occur,
the DS1873 writes the whole EEPROM memory page,
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page
is written, bytes on the page that were not modified
during the transaction are still subject to a write
cycle. This can result in a whole page being worn out
over time by writing a single byte repeatedly. Writing
a page one byte at a time wears the EEPROM out
eight times faster than writing the entire page at
once. The DS1873’s EEPROM write cycles are speci-
fied in the Nonvolatile Memory Characteristics table.
The specification shown is at the worst-case temper-
ature. It can handle approximately ten times that
many writes at room temperature. Writing to SRAM-
shadowed EEPROM memory with SEEB = 1 does not
count as an EEPROM write cycle when evaluating
the EEPROM’s estimated lifetime.
Reading a single byte from a slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the
slave, the master generates a START condition,
writes the slave address byte with R/W = 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master
generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated
W
______________________________________________________________________________________
) after the STOP condition to write the contents of
W
to elapse
The DS1873 features nine separate memory tables that
are internally organized into 8-byte rows.
The DS1873 has two passwords that are each 4 bytes
long. The lower level password (PW1) has all the
access of a normal user plus those made available with
PW1. The higher level password (PW2) has all the
access of PW1 plus those made available with PW2.
The values of the passwords reside in EEPROM inside
of PW2 memory. At power-up, all PWE bits are set to 1,
and all reads at this location are 0.
The Lower Memory is addressed from 00h to 7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the table-select byte.
Table 01h primarily contains user EEPROM (with PW1
level access) as well as alarm and warning-enable
bytes.
Table 02h is a multifunction space that contains config-
uration registers, scaling and offset values, passwords,
interrupt registers as well as other miscellaneous con-
trol bytes.
Table 04h contains a temperature-indexed LUT for
control of the modulation output. The modulation LUT
can be programmed in 2°C increments over the -40°C
to +102°C range. The table also contains a tempera-
ture-indexed LUT for MOD offsets.
Table 05h is empty by default. It can be configured to
contain the alarm- and warning-enable bytes from Table
01h, Registers F8h–FFh with the MASK bit enabled
(Table 02h, Register 89h). In this case Table 01h is
empty.
Table 06h contains a temperature-indexed LUT that
allows the APC set point to change as a function of
temperature to compensate for tracking error (TE). The
APC LUT has 36 entries that determine the APC setting
in 4°C windows between -40°C and +100°C. The table
also contains a temperature-indexed LUT for HBIAS
thresholds.
Table 07h contains a temperature-indexed LUT for con-
trol of DAC1. The LUT has 72 entries that determine the
DAC setting in 4°C windows between -40°C and
+100°C. The table also contains a temperature-indexed
LUT for DAC1 offsets.
START condition, writes the slave address byte (R/W
= 1), reads data with ACK or NACK as applicable,
and generates a STOP condition.
Memory Organization