DS1873T+ Maxim Integrated Products, DS1873T+ Datasheet - Page 8

• Manufacturer Part Number: DS1873T+
• Description: IC CTLR SFP+ ANLG LDD 28-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controllerr

Specifications of DS1873T+

• Number Of Channels: 1
• Voltage - Supply: 2.85 V ~ 3.9 V
• Current - Supply: 2.5mA
• Operating Temperature: -40°C ~ 95°C
• Package / Case: 28-WFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1873T+000

I
(V
SFP+ Controller with Analog LDD Interface
NONVOLATILE MEMORY CHARACTERISTICS
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: I
Note 11: C
Note 12: EEPROM write begins after a STOP condition occurs.
8
2
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP and START
Condition
START Hold Time
START Setup Time
Data Out Hold Time
Data In Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
STOP Setup Time
EEPROM Write Time
Capacitive Load for Each Bus Line
EEPROM Write Cycles
CC
CC
C AC ELECTRICAL CHARACTERISTICS
_______________________________________________________________________________________
= +2.85V to +3.9V, T
= +2.85V to +3.9V, unless otherwise noted.)
PARAMETER
All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Inputs are at supply rail. Outputs are not loaded.
This parameter is guaranteed by design.
Full-scale is user programmable.
A temperature conversion is completed and the MOD DAC value is recalled from the LUT and V
be above VCC LO alarm.
The sampling time is 1.6µs per cycle. Each input is sampled every 8 cycles.
This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias output will be within 3% within the time specified by the binary search time. See the BIAS and MOD Output
Control During Power-Up section.
timing.
2
C interface timing shown is for fast mode (400kHz). This device is also backward compatible with I
B
—the total capacitance of one bus line in pF.
PARAMETER
A
= -40°C to +95°C, timing referenced to V
SYMBOL
SYMBOL
t
t
t
t
t
HD:STA
HD:DAT
SU:DAT
SU:STO
SU:STA
t
t
f
HIGH
t
LOW
t
SCL
BUF
C
At +25°C
At +85°C
WR
t
t
R
F
B
(Note 10)
(Note 11)
(Note 11)
(Note 12)
CONDITIONS
CONDITIONS
IL(MAX)
and V
IH(MIN)
, unless otherwise noted.) (See Figure 16.)
20 + 0.1C
20 + 0.1C
200,000
MIN
100
50,000
1.3
0.6
1.3
0.6
0.6
0.6
MIN
0
0
B
B
TYP
CC
TYP
has been measured to
2
C standard mode
MAX
MAX
400
300
300
400
0.9
20
UNITS
UNITS
kHz
ms
pF
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs