A6281EESTR-T Allegro Microsystems Inc, A6281EESTR-T Datasheet
A6281EESTR-T
Specifications of A6281EESTR-T
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A6281EESTR-T Summary of contents
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Features and Benefits ▪ 3 × 10-bit PWM brightness settings ▪ 3 × 7-bit dot correction current settings ▪ operation ▪ Wide output current range 150 mA per channel ▪ Internally generated PWM clock ...
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... Applications include: ▪ Colored, large-character LED signs ▪ Scrolling, colored marquees Selection Guide Part Number Packing* A6281EESTR-T 1500 pieces/reel *Contact Allegro for additional packing options. Absolute Maximum Ratings Characteristic Load Supply Voltage Output Voltage Output Current ...
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A6281 SDI CI LI 800 kHz Clock To PWM Counters OEI REXT R VIN EXT Regulator VREG Terminal List Table Number Name 1 REXT An external resistor at this terminal establishes maximum output current 2 VREG Regulator decoupling 3 LGND ...
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A6281 OPERATING CHARACTERISTICS, valid at T Characteristic ELECTRICAL CHARACTERISTICS Quiescent Supply Current Operating Supply Current Load Supply Voltage Undervoltage Lockout VREG Voltage Range 1 Output Current (any single output) Output to Output Matching Error 2 Output Voltage Range Load Regulation ...
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A6281 0 CI (External Clock SDI D31 D30 (Serial Data In) SDO (Serial Data Out) LI (Latch In) LO (Latch Out) Internal Oscillator or CI (External Clock) PWM Counter I OUT0 Brightness Data P(OE) ...
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A6281 Shift Register The A6281 has a 32-bit shift register that loads data through the SDI (serial data in) pin. The shift register operates by a first-in first-out (FIFO) method. The most significant bit (MSB, bit 31) is the first ...
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A6281 The relationship of the PWM value to the output duty cycle is n given in the following table: PWM Duty Cycle n 0 0/1024 ( 2/1024 2 3/1024 . . . . . . 1023 1024/1024 (100 ...
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A6281 intended as an external power source. There should be a 1.0 μ ceramic capacitor connected between the V REG pin and LGND. The capacitor should be located as close to the V REG pin as possible. Dot ...
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A6281 Timing Considerations A6281s can be used in large numbers to drive many LEDs with the control signals connected serially together using short cables between each pixel (see figure 8). Because the clock negative edge drives the data to the ...
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A6281 8 μF – System Logic Clock Data Latch Output Enable Tie LGND and PGND to PAD externally Figure 8. Application driving 3 RGB LED strings, each maximum + μF – ...
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A6281 3.00 ±0. 17X 0.08 C +0.05 0.25 –0.07 0.50 +0.15 0.40 –0. 1.70 Copyright ©2006-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or ...