A6276ELPTR-T Allegro Microsystems Inc, A6276ELPTR-T Datasheet - Page 8

• Manufacturer Part Number: A6276ELPTR-T
• Description: IC LED DRIVER LINEAR 24-TSSOP
• Manufacturer: Allegro Microsystems Inc
• Type: Linear (Non-Switching)r

Specifications of A6276ELPTR-T

• Constant Current: Yes
• Topology: 16-Bit Shift Register
• Number Of Outputs: 16
• Internal Driver: Yes
• Type - Primary: General Purpose
• Frequency: 20MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Voltage - Output: 1V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 75.5mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -

register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data in-
formation towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
respective latch when the LATCH ENABLE is high (serial-to-
par al lel con ver sion). The latches continue to accept new data as
DATA OUT
A6276
OUTPUT
OUTPUT
ENABLE
ENABLE
ENABLE
DATA IN
SERIAL
SERIAL
CLOCK
LATCH
Serial data present at the input is transferred to the shift
Information present at any register is transferred to the
OUT
OUT
N
N
A
DATA
50%
B
t
p
C
50%
LOW = ALL OUTPUTS ENABLED
D
50%
50%
F
t
TIMING REQUIREMENTS and SPECIFICATIONS
pHL
50%
HIGH = ALL OUTPUTS DISABLED (BLANKED)
E
90%
t
p
t
pLH
DATA
(Logic Levels are V
t
DATA
f
50%
HIGH = OUTPUT OFF
LOW = OUTPUT ON
t
r
16-Bit Serial Input, Constant-Current
Dwg. WP-030-1A
10%
Dwg. WP-029-1
50%
DATA
long as the LATCH ENABLE is held high. Ap pli ca tions where
the latches are bypassed (LATCH ENABLE tied high) will
require that the OUTPUT EN ABLE input be high during serial
data entry.
driv ers are disabled (OFF). The in for ma tion stored in the latches
is not affected by the OUTPUT ENABLE input. With the OUT-
PUT ENABLE input low, the outputs are con trolled by the state
of their re spec tive latches.
DD
and Ground)
When the OUTPUT ENABLE input is high, the output sink
A. Data Active Time Before Clock Pulse
B. Data Active Time After Clock Pulse
C. Clock Pulse Width, t
D. Time Between Clock Ac ti va tion
E. Latch Enable Pulse Width, t
F. Output Enable Pulse Width, t
NOTE: Timing is representative of a 10 MHz clock. Sig-
nif i cant ly higher speeds are attainable.
Max. Clock Transition Time, t
(Data Set-Up Time), t
(Data Hold Time), t
and Latch Enable, t
Latched LED Driver
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
w(CK)
su(L)
h(D)
su(D)
.................................. 50 ns
................................. 20 ns
............................... 100 ns
r
w(L)
or t
w(OE)
............................. 50 ns
f
...................... 100 ns
....................... 10 μs
................... 4.5 μs
7