CAT3636HV3-GT2 ON Semiconductor, CAT3636HV3-GT2 Datasheet - Page 9

• Manufacturer Part Number: CAT3636HV3-GT2
• Description: IC LED DVR 6CH QUAD MODE 16TQFN
• Manufacturer: ON Semiconductor
• Series: QUAD-Mode®r
• Type: Backlight, White LEDr

Specifications of CAT3636HV3-GT2

• Topology: Linear (LDO), Switched Capacitor (Charge Pump)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz ~ 1.4MHz
• Voltage - Supply: 2.5 V ~ 5.5 V
• Voltage - Output: 7V
• Mounting Type: Surface Mount
• Package / Case: 16-TFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 32mA
• Internal Switch(s): Yes
• Efficiency: 92%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LED Current Setting
programmed through the 1−wire EN/SET digital control
input. By pulsing this signal according to a specific protocol,
a set of internal registers can be addressed and written into
allowing to configure each bank of LEDs with the desired
current. There are six registers: the first five are 4 bits long
and the sixth is 1 bit long. The registers are programmed by
first selecting the register address and then programming
data into that register.
identify the address and data. The address is serially
programmed adhering to low and high duration time delays.
One down pulse corresponds to register 1 being selected.
Two down pulses correspond to register 2 being selected and
so on up to register 6. T
100 ms. Anything below 200 ns may be ignored.
programmed, the user must wait 500 ms to 1000 ms before
programming the first data pulse falling edge. If the falling
edge of the data is not received within 1000 ms, the device
will revert back to waiting for an address.
The current in each of the six LED channels is
An internal counter records the number of falling edges to
Once the final rising edge of the address pointer is
LO
and T
Figure 21. EN/SET One Wire Addressable Timing Diagram
HI
must be within 200 ns to
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pointer. If a register is selected but no data is programmed,
then the register value is reset back to its initial default value
with all data bits to 0.
programmed, the user must wait 1.5 ms before
programming another address. If programming fails or is
interrupted, the user must wait T
last rising edge before reprogramming can commence.
for an address. The device requires a minimum 10 ms delay
(T
power−up. After this time delay, the device registers may be
programmed adhering to the timing constraints shown in
Figure 21. If no falling edge is detected within 100 ms of
power−up, then the user must wait 2 ms before trying to
program the device again.
sources, the EN/SET input should be kept low for a duration
T
with a delay of about 1 ms. All register data are lost.
OFF
Data in a register is reset once it is selected by the address
Once the final rising edge of the data pulses is
Upon power−up, the device automatically starts looking
To power−down the device and turn−off all current
SETUP
of 1.5 ms or more. The driver typically powers−down
) to ensure the initialization of the internal logic at
RESETDELAY
2 ms from the