MAX7302ATE+T Maxim Integrated Products, MAX7302ATE+T Datasheet - Page 3
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MAX7302ATE+T
Manufacturer Part Number
MAX7302ATE+T
Description
IC LED DRIVER LINEAR 16-TQFN
Manufacturer
Maxim Integrated Products
Type
Linear (I²C Interface)r
Datasheet
1.MAX7302AEE.pdf
(30 pages)
Specifications of MAX7302ATE+T
Topology
Open Drain, PWM
Number Of Outputs
9
Internal Driver
Yes
Type - Primary
Backlight, LED Blinker
Type - Secondary
White LED
Frequency
1MHz
Voltage - Supply
1.62 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Operating Temperature
-40°C ~ 125°C
Current - Output / Channel
25mA
Internal Switch(s)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Efficiency
-
Lead Free Status / Rohs Status
Details
PORT, INTERRUPT (INT), AND RESET (RST) TIMING CHARACTERISTICS
(V
(Figures 10, 15, 16 and 17)
SERIAL INTERFACE TIMING CHARACTERISTICS
(V
(Figure 10)
Note 1: All parameters are tested at T
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
Note 4: C
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 6: A startup time is required for the internal oscilator to start if it is not running already.
Oscillator Frequency
Port Output Data Valid High Time
Port Output Data Valid Low Time (Note 6)
Port Input Setup Time
Port Input Hold Time
CLA Rise Time P5, P9 as Push-Pull Outputs
CLA Fall Time P5, P9 as Push-Pull Outputs
CLA Propagation Delay P2, P3, or P4 to P5; P6, P7,
or P8 to P9
INT Input Data Valid Time
INT Reset Delay Time from Acknowledge
RST Rising to START Condition Setup Time
RST Pulse Width
Serial-Clock Frequency
Bus Timeout
Bus Fr ee Tim e Betw een a S TOP and a S TART C ond i ti on
Hold Time, (Repeated) START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting
Pulse Width of Spike Suppressed
C ap aci ti ve Load for E ach Bus Li ne
DD
DD
Level-Translating GPIO and LED Driver with CLA
= 1.62V to 3.6V, T
= 1.62V to 3.6V, T
undefined region of SCL’s falling edge.
b
= total capacitance of one bus line in pF. t
PARAMETER
PARAMETER
_______________________________________________________________________________________
A
A
= T
= T
MIN
MIN
to T
to T
MAX
MAX
A
= +25°C. Specifications over temperature are guaranteed by design.
, unless otherwise noted. Typical values are at V
, unless otherwise noted. Typical values are at V
R
SYMBOL
SMBus/I
SYMBOL
t
TIMEOUT
t
t
t
t
t
t
t
and t
HD,DAT
PDCLA
HD,STA
SU,STO
SU,DAT
t
RFCLA
SU,STA
t
t
f
t
t
PPVH
t
PPVL
f
t
HIGH
t
CLK
PSU
t
LOW
RST
SCL
BUF
F.TX
t
t
t
t
C
PH
t
t
SP
IV
IR
W
R
F
b
F
are measured between 0.3 x V
f
f
C
C
C
C
C
C
C
C
(Note 3)
(Notes 2, 4)
(Notes 2, 4)
(Note 4)
(Note 5)
(Note 2)
CLK
C LK
L
L
L
L
L
L
L
L
≤ 100pF
≤ 100pF (Note 2)
= 100pF
= 100pF
= 100pF, V
= 100pF, V
= 100pF
= 100pF
= internal oscillator
= OS C IN exter nal i np ut
CONDITIONS
CONDITIONS
2
C Interfaced 9-Port,
LA
LA
≥ 2.7V
≥ 2.7V
DD
DD
= 3.3V, V
= 3.3V, V
DD
and 0.7 x V
MIN
900
500
MIN
100
1.3
0.6
0.6
0.6
1.3
0.7
0
4
IL
LA
LA
of the SCL signal) to bridge the
20 + 0.1C
20 + 0.1C
20 + 0.1C
= 3.3V, T
= 3.3V, T
TYP
17
TYP
32
14
28
DD
31
50
.
A
A
b
b
b
= +25°C.) (Note 1)
= +25°C.) (Note 1)
1/f
MAX
MAX
50
400
300
300
250
400
0.9
CLK
1
4
4
4
UNITS
UNITS
MHz
kHz
kHz
ms
pF
µs
µs
µs
ns
ns
µs
µs
ns
ns
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
ns
s
3