MAX7302ATE+ Maxim Integrated Products, MAX7302ATE+ Datasheet - Page 18

IC LED DRIVER LINEAR 16-TQFN

MAX7302ATE+

Manufacturer Part Number
MAX7302ATE+
Description
IC LED DRIVER LINEAR 16-TQFN
Manufacturer
Maxim Integrated Products
Type
Linear (I²C Interface)r
Datasheet

Specifications of MAX7302ATE+

Topology
Open Drain, PWM
Number Of Outputs
9
Internal Driver
Yes
Type - Primary
Backlight, LED Blinker
Type - Secondary
White LED
Frequency
1MHz
Voltage - Supply
1.62 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
16-TQFN Exposed Pad
Operating Temperature
-40°C ~ 125°C
Current - Output / Channel
25mA
Internal Switch(s)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Efficiency
-
Lead Free Status / Rohs Status
 Details
SMBus/I
Level-Translating GPIO and LED Driver with CLA
Table 12. CLA0 (P2–P5) Configuration Register Setting (0x28) (continued)
Table 13. Output P5 Configuration
Table 14. CLA1 (P6–P9) Configuration Register Setting (0x29)
18
XOR noninverted
XOR P7 inverted
XOR P6 inverted
XOR both ports inverted
3 input AND/OR all noninverted
3 input AND/OR P6 inverted
3 input AND/OR P7 inverted
3 input AND/OR P8 inverted
3 input AND/OR P6 and P7 inverted
3 input AND/OR P6 and P8 inverted
3 input AND/OR P7 and P8 inverted
3 input AND/OR all inverted
2 input AND/OR P6 and P7 noninverted
2 input AND/OR P6 and P7 inverted
2 input AND/OR P6 inverted and P7
2 input AND/OR P6 and P7 both inverted
2 input AND/OR P2 and P3 noninverted
2 input AND/OR P2 and P3 inverted
2 input AND/OR P2 inverted and P3
2 input AND/OR P2 and P3 both inverted
2 input AND/OR P2 and P4 noninverted
2 input AND/OR P2 and P4 inverted
2 input AND/OR P2 inverted and P4
2 input AND/OR P2 and P4 both inverted
2 input AND/OR P3 and P4 noninverted
2 input AND/OR P3 and P4 inverted
2 input AND/OR P3 inverted and P4
2 input AND/OR P3 and P4 both inverted
BIT
D7
D6
______________________________________________________________________________________
LOGIC LEVEL
0
1
0
1
2
C Interfaced 9-Port,
FUNCTION
FUNCTION
Output not cascaded to CLA1
Output cascaded to CLA1
Output noninverted
Output inverted
FUNCTION
D5
D5
0
1
0
0
1
1
D4
D4
1
0
0
0
0
1
1
1
1
X
X
0
1
0
1
0
0
1
1
REGISTER BIT
REGISTER BIT
D3
D3
X
1
1
1
0
1
D2
D2
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
X
0
1
0
1
0
1
0
1
D1
D1
X
1
1
1
1
0
D0
D0
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
X

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