MAX7302ATE+ Maxim Integrated Products, MAX7302ATE+ Datasheet - Page 22

• Manufacturer Part Number: MAX7302ATE+
• Description: IC LED DRIVER LINEAR 16-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Linear (I²C Interface)r

Specifications of MAX7302ATE+

• Topology: Open Drain, PWM
• Number Of Outputs: 9
• Internal Driver: Yes
• Type - Primary: Backlight, LED Blinker
• Type - Secondary: White LED
• Frequency: 1MHz
• Voltage - Supply: 1.62 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 25mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / Rohs Status: Details

SMBus/I
Level-Translating GPIO and LED Driver with CLA
The MAX7302 operates as a slave that sends and
receives data through an I
face. The interface uses a serial-data line (SDA) and a
serial-clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7302 and generates the SCL clock that
synchronizes the data transfer (see Figure 10).
The MAX7302 SDA line operates as both an input and
an open-drain output. A 4.7kΩ (typ) pullup resistor is
required on SDA. The MAX7302 SCL line operates only
as an input. A 4.7kΩ (typ) pullup resistor is required on
SCL if there are multiple masters on the 2-wire inter-
face, or if the master in a single-master system has an
open-drain SCL output.
Figure 10. 2-Wire Serial Interface Timing Details
Figure 11. START and STOP Conditions
22
SDA
SCL
CONDITION
______________________________________________________________________________________
START
S
RESET
SDA
SCL
t
HD,STA
START CONDITION
2
C Interfaced 9-Port,
t
LOW
2
C-compatible, 2-wire inter-
t
Serial Interface
R
t
SU,DAT
t
Serial Addressing
HIGH
t
F
t
HD,DAT
CONDITION
STOP
P
t
REPEATED START CONDITION
SU,STA
Each transmission consists of a START condition (see
Figure 11) sent by a master, followed by the MAX7302
7-bit slave address plus R/W bit, a register address byte,
one or more data bytes, and finally a STOP condition
(see Figure 11).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (see Figure 11).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(see Figure 12).
Figure 12. Bit Transfer
SDA
SCL
t
WL(RST)
t
HD,STA
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
START and STOP Conditions
ALLOWED
t
SU,STO
CONDITION
STOP
t
BUF
CONDITION
START
Bit Transfer