ISL6605CRZ Intersil, ISL6605CRZ Datasheet - Page 5

• Manufacturer Part Number: ISL6605CRZ
• Description: IC DRIVER MOSFET DUAL SYNC 8QFN
• Manufacturer: Intersil

Specifications of ISL6605CRZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 33V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -

Functional Pin Description
Note: Pin numbers refer to the SOIC package. Check
PINOUT diagrams for QFN pin numbers.
UGATE (Pin 1)
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see the
three-state PWM Input section under DESCRIPTION for further
details). Connect this pin to the PWM output of the controller.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
EN (Pin 7)
Enable input pin. Connect this pin to HIGH to enable and
LOW to disable the IC. When disabled, the IC draws less
than 1μA bias current.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. This pin provides a return path
for the upper gate driver.
Timing Diagram
t
PDLLGATE
UGATE
LGATE
PWM
t
PDHUGATE
5
t
FLGATE
t
RUGATE
ISL6605
t
PDLUGATE
Thermal Pad (in QFN only)
In the QFN package, the pad underneath the center of the
IC is a thermal substrate. The PCB “thermal land” design
for this exposed die pad should include thermal vias that
drop down and connect to one or more buried copper
plane(s). This combination of vias for vertical heat escape
and buried planes for heat spreading allows the QFN to
achieve its full thermal potential. This pad should be either
grounded or floating, and it should not be connected to
other nodes. Refer to TB389 for design guidelines.
Description
Operation
Designed for speed, the ISL6605 MOSFET driver controls both
high-side and low-side N-Channel FETs from one externally
provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
times [t
section. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[t
drops below 1V. This prevents both the lower and upper
MOSFETs from conducting simultaneously or shoot-
through. Once this delay period is completed the upper gate
drive begins to rise [t
on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
upper gate begins to fall [t
shoot-through circuitry determines the lower gate delay time,
t
and the lower gate is allowed to rise after the upper MOSFET
gate-to-source voltage drops below 1V. The lower gate then
rises [t
PDHLGATE
PDHUGATE
RLGATE
PDLLGATE
FLGATE
. The upper MOSFET gate voltage is monitored
] based on how quickly the LGATE voltage
], turning on the lower MOSFET.
] are provided in the Electrical Specifications
t
PDHLGATE
], the lower gate begins to fall. Typical fall
PDLUGATE
RUGATE
t
FUGATE
FUGATE
] and the upper MOSFET turns
] is encountered before the
]. Again, the adaptive
t
RLGATE
May 9, 2006
FN9091.7