LTC1255CS8 Linear Technology, LTC1255CS8 Datasheet - Page 6

• Manufacturer Part Number: LTC1255CS8
• Description: IC MOSFET DVR HI-SIDE DUAL 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1255CS8

• Configuration: High-Side
• Input Type: Non-Inverting
• Delay Time: 180µs
• Number Of Configurations: 2
• Number Of Outputs: 2
• Voltage - Supply: 9 V ~ 24 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Peak: -
• High Side Voltage - Max (bootstrap): -

OPERATIO
BLOCK DIAGRA
LTC1255
Internal Voltage Regulation
The output of the TTL-to-CMOS converter drives two
regulated supplies which power the low voltage CMOS
logic and analog blocks. The regulator outputs are isolated
from each other so that the noise generated by the charge
pump logic is not coupled into the 100mV reference or the
analog comparator.
Gate Charge Pump
Gate drive for the power MOSFET is produced by an
adaptive charge pump circuit which generates a gate
voltage substantially higher than the power supply volt-
age. The charge pump capacitors are included on-chip and
therefore no external components are required to generate
the gate drive. The charge pump is designed to drive a 12V
Zener diode clamp connected across the gate and source
of the MOSFET switch.
6
INPUT
LOW STANDBY
TTL-TO-CMOS
REGULATOR
CONVERTER
CURRENT
GND
V
S
U
ANALOG
ANALOG SECTION
W
REGULATOR
REFERENCE
VOLTAGE
100mV
(One Channel)
DIGITAL
COMP
SHOT
ONE
DELAY
10 s
Drain Current Sense
The LTC1255 is configured to sense the current flowing
into the drain of the power MOSFET in a high-side applica-
tion. An internal 100mV reference is compared to the drop
across a sense resistor (typically 0.002
series with the drain lead. If the drop across this resistor
exceeds the internal 100mV threshold, the input latch is
reset and the gate is quickly discharged via a relatively
large N-channel transistor.
Controlled Gate Rise and Fall Times
When the input is switched ON and OFF, the gate is
charged by the internal charge pump and discharged in a
controlled manner. The charge and discharge rates have
been set to minimize RFI and EMI emissions in normal
operation. If a short circuit or current overload condition
is encountered, the gate is discharged very quickly (typi-
cally a few microseconds) by a large N-channel transistor.
R
S
LATCH
INPUT
AND DISCHARGE
CONTROL LOGIC
GATE CHARGE
AND CHARGE
OSCILLATOR
PUMP
GATE CHARGE
FAST/SLOW
LOGIC
to 0.10 ) in
LTC1255 • BD
DRAIN
SENSE
GATE