IR2214SSTRPBF International Rectifier, IR2214SSTRPBF Datasheet - Page 15

• Manufacturer Part Number: IR2214SSTRPBF
• Description: IC DVR HALF BRIDGE IC 24SSOP
• Manufacturer: International Rectifier

Specifications of IR2214SSTRPBF

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 440ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 1200V
• Voltage - Supply: 11.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Family Hvic: General Purpose HVICs
• Channels: 2
• Topology: Half Bridge
• Application: General Purpose / Motor Control
• Voffset: 1200
• Io+ (ma): 2000
• Io- (ma): 3000
• Separate Power And Logic Ground: Yes
• Uvlo: Vcc / Vbs
• Vbsuv+ / Vccuv+ Min (v): 9.3
• Vbsuv+ / Vccuv+ Typ (v): 10.2
• Vbsuv+ / Vccuv+ Max (v): 11.4
• Vbsuv- / Vccuv- Min (v): 8.7
• Vbsuv- / Vccuv- Typ (v): 9.3
• Vbsuv- / Vccuv- Max (v): 10.3
• Dt / Sdt Min (ns): 5700
• Dt / Sdt Typ (ns): 9250
• Dt / Sdt Max (ns): 13500
• T On Min (ns): 220
• T On Typ (ns): 440
• T On Max (ns): 660
• T Off Min (ns): 220
• T Off Typ (ns): 440
• T Off Max (ns): 660
• Fault Reporting: Yes
• Package: 24 Lead
• Part Status: Active & Preferred
• Special Features: Soft Shutdown and Desaturation Detection
• For Use With: IRMD2214SS - KIT DESIGN EVAL BOARD IR2214SS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.irf.com
Referred to the timing diagram of Fig. 17:
A.
B.
C. When
D. The DSH goes high but this is not read
E.
F.
G.
When the input signals are on together the
outputs go off (anti-shoot through),
The HO signal is on and the high side IGBT
desaturates, the HO turn off softly while the
SY_FLT stays low. When SY_FLT goes high
the FAULT/SD goes low. While in SSD, if LIN
goes up, LO does not change (freeze),
FAULT/SD section) FLT_CLR can disable it
and the outputs go back to follow the inputs,
because HO is off,
The LO signal is on and the low side IGBT
desaturates, the low side behaviour is the
same as described in point B,
The DSL goes high but this is not read as LO
is off,
As point A (anti-shoot through
FAULT/SD
HO(HOP/HON)
LO(LOP/LON)
FAULT/SD
FLT_CLR
Figure 17: I/O Timing Diagram with SY_FLT and FAULT/SD as Output
HO (HOP/HON)
SY_FLT
LO (LOP/LON)
Figure 18: I/O Logic Diagram with SY_FLT and FAULT/SD as Input
DSL
DSH
HIN
LIN
FAULT/SD
is
FLT_CLR
SY_FLT
latched
HIN
LIN
).
A
low
B
(see
A B
15
C
C
Referred to the timing diagram Fig. 18:
D
D
A.
B.
C. Externally driven low FAULT/SD (shutdown
D. The FAULT/SD is released and the outputs go
E.
F.
E
The device is in the hold state, regardless of
input variations. The hold state results as
SY_FLT is forced low externally,
The device outputs go off by hard shutdown,
externally commanded. A through B is the
same sequence adopted by another IR2x14x
device in SSD procedure.
state) cannot be disabled by forcing FLT_CLR
(see FAULT/SD section),
back to follow the inputs,
Externally driven low FAULT/SD: outputs go
off by hard shutdown (like point B),
As point A and B but for the low side output.
E
F
IR2114/IR2214SSPbF
F
© 2009 International Rectifier
G