ISL6622AIRZ Intersil, ISL6622AIRZ Datasheet - Page 7

• Manufacturer Part Number: ISL6622AIRZ
• Description: IC MOSFET DRVR SYNC BUCK 10-DFN
• Manufacturer: Intersil

Specifications of ISL6622AIRZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 1.25A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

protection to the load if the upper MOSFET(s) is or becomes
shorted. If the PHASE node goes higher than the gate
threshold of the lower MOSFET, it results in the progressive
turn-on of the device and the effective clamping of the PHASE
node’s rise. The actual PHASE node clamping level depends
on the lower MOSFET’s electrical characteristics, as well as the
characteristics of the input supply and the path connecting it to
the respective PHASE node.
Internal Bootstrap Device
The ISL6622A features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the BOOT to PHASE pins.
The bootstrap capacitor must have a maximum voltage
rating well above the maximum voltage intended for UVCC.
Its minimum capacitance value can be chosen from
Equation 1.
where Q
at V
control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive. Select
results are exemplified in Figure 2.
Gate Drive Voltage Versatility
The ISL6622A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The ISL6622A
C
Q
BOOT_CAP
GATE
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
GS1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
=
G1
0.0
gate-source voltage and N
Q
----------------------------------- - N
20nC
G1
is the amount of gate charge per upper MOSFET
≥
0.1
V
VOLTAGE
------------------------------------- -
ΔV
•
GS1
UVCC
BOOT_CAP
Q
0.2
GATE
50nC
Q
GATE
•
0.3
Q1
BOOT_CAP
= 100nC
ΔV
0.4
BOOT_CAP
7
0.5
Q1
0.6
term is defined as the
is the number of
(V)
0.7
0.8
0.9
(EQ. 1)
1.0
ISL6622A
upper gate drive is fixed to VCC [+12V] in the SOIC, but the
lower drive rail can be driven from 5V to 12V using the LVCC
pin. In the DFN package, a separate UVCC pin is available
for the upper gate drive voltage to be driven from 5V to 12V
for efficiency optimization, while the lower gate can be driven
independently using the LVCC pin from 5V to 12V.
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6622A detects the zero current crossing of the output
inductor and turns off LGATE. This prevents the low side
MOSFET from sinking current and ensures that
discontinuous conduction mode (DCM) is achieved. The
LGATE has a minimum on-time of 350ns in DCM mode.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
external gate resistance, and the selected MOSFET’s internal
gate resistance and total gate charge. Calculating the power
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level may push the IC beyond the maximum
recommended operating junction temperature. The DFN
package is more suitable for high frequency applications. See
“Layout Considerations” on page 8 for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation is
used to ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses due to
the gate charge of MOSFETs and the driver’s internal circuitry
and their corresponding average driver current can be
estimated with Equations 2 and 3, respectively:
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
and N
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
product is the quiescent power of the driver without
capacitive load.
P
I
DR
Qg_TOT
P
P
=
Qg_Q2
Qg_Q1
Q2
⎛
⎜
⎝
Q
----------------------------------------------------- -
are number of upper and lower MOSFETs,
G1
=
P
=
=
•
Qg_Q1
UVCC N
V
Q
-------------------------------------- - F
Q
------------------------------------- - F
GS1
G1
G2
V
V
•
•
+
GS2
GS1
•
LVCC
UVCC
P
SW
Qg_Q2
Q1
), the output drive impedance, the
G1
+
2
2
•
Q
---------------------------------------------------- -
and Q
•
+
G2
I
SW
Q
SW
•
•
LVCC N
•
VCC
V
G2
GS1
•
N
GS2
N
Q
Q2
) is defined at a
Q1
and V
is the driver’s total
•
Q2
GS2
⎞
⎟
⎠
Q*
•
VCC
) in the
F
March 19, 2009
SW
FN6601.2
(EQ. 2)
(EQ. 3)
Q1
+
I
Q