ISL6622BCRZ Intersil, ISL6622BCRZ Datasheet - Page 5

• Manufacturer Part Number: ISL6622BCRZ
• Description: IC MOSFET DRVR SYNC BUCK 10-DFN
• Manufacturer: Intersil

Specifications of ISL6622BCRZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 1.25A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
Functional Pin Description
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
Tristate Low Delay
Minimum LGATE ON-Time During PSI Operation
OUTPUT (Note 4)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
PACKAGE PIN #
SOIC
1
2
3
4
5
6
7
8
-
-
-
DFN
10
11
1
2
3
4
5
6
7
8
9
PARAMETER
SYMBOL
GD_SEL
PHASE
UGATE
LGATE
BOOT
UVCC
LVCC
PWM
GND
VCC
PAD
PIN
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
This pin sets the LG drive voltage.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output
of the controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
This pin provides power for the LGATE drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to the upper gate drive. Its operating range is +5V to +12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC and to the LDO for the
lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
R
R
t
I
I
U_SOURCE
LG_ON_DM
L_SOURCE
SYMBOL
U_SOURCE
L_SOURCE
R
R
I
I
U_SINK
t
L_SINK
t
t
t
t
U_SINK
L_SINK
PDHU
PDHL
PDLU
PDLL
TSLD
t
t
t
t
RU
RL
FU
FL
ISL6622B
V
V
V
V
V
V
V
V
V
V
V
20mA Source Current
V
20mA Sink Current
V
20mA Source Current
V
20mA Sink Current
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
= 12V, 3nF Load
= 12V
= 12V
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
TEST CONDITIONS
FUNCTION
MIN
230
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
1.25
1.35
1.35
0.90
330
2.0
26
18
18
12
20
10
10
10
60
2
2
3
MAX
450
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
March 19, 2009
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ω
Ω
Ω
Ω
A
A
A
A