HIP4083ABT Intersil, HIP4083ABT Datasheet - Page 4

• Manufacturer Part Number: HIP4083ABT
• Description: IC DRIVER HISIDE N-CH 3PH 16SOIC
• Manufacturer: Intersil

Specifications of HIP4083ABT

• Configuration: 3 Phase Bridge
• Input Type: PWM
• Delay Time: 65ns
• Number Of Configurations: 1
• Number Of Outputs: 3
• High Side Voltage - Max (bootstrap): 95V
• Voltage - Supply: 7 V ~ 15 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Peak: -

Typical Application: High Side Switch
Pin Descriptions
NUMBER
PIN
11
16
13
10
15
14
12
6
1
2
3
5
4
7
8
9
SYMBOL
UVLO
(xHO)
(xHB)
(xHS)
(xHI)
AHO
BHO
CHO
AHB
BHB
CHB
AHS
BHS
CHS
V
V
CHI
AHI
BHI
DIS
SS
DD
PROCESSOR
MICRO-
Gate driver supplies. One external bootstrap diode and one capacitor are required for each. The bootstrap diode
and capacitor may be omitted when the HIP4083 is used to drive the lower gates in three phase full bridge
applications. In this case, tie all three xHB pins to V
full bridge applications, the lower FETs must be turned on first at start up to refresh the bootstrap capacitors. In
high side switch applications, the load will keep xHS low and refresh should happen automatically at start up.
Logic level inputs. Logic at these three pins controls the three output drivers, AHO, BHO and CHO. When xHI is
low, xHO is high. When xHI is high, xHO is low. DIS (Disable) overrides all input signals. xHI can be driven by
signal levels of 0V to 15V (no greater than V
Chip ground.
Undervoltage setting. A resistor can be connected between this pin and V
point - see Figure 7. With this pin not connected the undervoltage set point is typically 7V. When this pin is tied to
V
Disable input. Logic level input that when taken high sets all three outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to
15V (no greater than V
Gate connections. Connect to the gates of the power MOSFETs in each phase.
MOSFET source connection. Connect the sources of the power MOSFETs and the negative side of the bootstrap
capacitors to these pins. In high side switch applications, 2mA of current will flow out of these pins into the load
when the upper FETs are off. This current is necessary to guarantee that the upper FETs stay off. This current
tends to pull xHS high. For proper refresh, the load must pull the voltage on xHS down to at least 7V below V
For example, when V
proper refresh is given by the following equation: R
impedance less than 5kΩ, refresh will happen automatically at start up.
Positive supply rail. Bypass this pin to V
V
simplifies the filtering requirements.
4
DD
DD
, the undervoltage set point is typically 6.2V.
are at the same potential, it is a good idea to run a separate line from the supply to each. This greatly
REFRESH
AHI
BHI
CHI
DIS
HIP4083
BOOT STRAP CAPACITOR
AND DIODE REQUIRED
GND
12V
DD
DD
).
= 12V, xHS must be pulled down to 5V. Therefore, the minimum load necessary for
AHO
BHO
CHO
HIP4083
HIP4083
SS
with a capacitor >1µF. In applications where the bus voltage and chip
DD
80V
).
DESCRIPTION
DD
MIN
and tie the xHS pins to the sources of the lower FETs. In
= 5V/2mA = 2.5kΩ. So in this case, if the load has an
SS
to program the under voltage set
LIGHT
DD
.