EL7156CSZ-T7 Intersil, EL7156CSZ-T7 Datasheet
EL7156CSZ-T7
Specifications of EL7156CSZ-T7
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EL7156CSZ-T7 Summary of contents
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... VL EL7156CS-T13 EL7156CSZ 5 VS- (Note) EL7156CSZ-T7 (Note) EL7156CSZ-T13 (Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil ...
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... Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C - -0.3V, V +0.3V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125° Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications ...
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Electrical Specifications +5V PARAMETER DESCRIPTION INPUT V Logic ‘1’ Input Voltage IH I Logic ‘1’ Input Current IH V Logic ‘0’ Input Voltage IL I Logic ‘0’ Input Current IL C Input Capacitance IN R ...
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Typical Performance Curves JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.0 PDIP8 θ = 100°C/W JA 0.8 0.6 SOIC8 0.4 θ = 160°C AMBIENT TEMPERATURE (°C) FIGURE 1. PACKAGE POWER DISSIPATION ...
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Typical Performance Curves C = 2000pF +25° d d SUPPLY VOLTAGE (V) FIGURE 7. PROPAGATION DELAY vs SUPPLY VOLTAGE +15V +25° ...
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Truth Table Timing Diagram INVERTED Standard Test Configuration 4.7µ 10kΩ 6 EL7156 Operating Voltage Range OUT Three-state V Three-state ...
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Pin Descriptions PIN NAME 1 VS+ Positive Supply Voltage 2 OE Output Enable 3 IN Input 4 GND Ground 5 VS- Negative Supply Voltage 6 VL Lower Output Voltage 7 OUT Output 8 VH High Output Voltage Block Diagram V ...
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Applications Information Product Description The EL7156 is a high performance 40MHz pin driver. It contains two analog switches connecting VH and VL to OUT. Depending on the value of the IN pin, one of the two switches will be closed ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...