CS1112YDWFR24 ON Semiconductor, CS1112YDWFR24 Datasheet - Page 7

• Manufacturer Part Number: CS1112YDWFR24
• Description: IC DRIVER QUAD PWR OUTPUT 24SOIC
• Manufacturer: ON Semiconductor
• Type: Low Sider

Specifications of CS1112YDWFR24

• Input Type: Non-Inverting
• Number Of Outputs: 4
• On-state Resistance: 1 Ohm
• Current - Output / Channel: 1A
• Current - Peak Output: 6A
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CS1112YDWFR24OSTR

harsh environments such as seen in an automobile system.
The device has four low–side switches all controlled
through an 8–bit Serial Peripheral Interface (SPI) port.
Control of the outputs is also OR’d with parallel inputs. This
is a critical feature enhancement over similar devices
because of the ease in which the parallel inputs can be used
to control the outputs in a Pulse Width Modulation (PWM)
mode. Creating a PWM mode using just the serial port input
is not a practical application.
process technology.
robustness of Bipolar with the dense logic capability of
CMOS, and the power capabilities of DMOS.
POWERSENSE in comparison to a bipolar technology. A
bipolar process requires DC bias currents to power–up the
integrated circuit. This is needed in many applications
requiring analog circuitry, but is not needed here. Digital
POWERSENSE logic dissipates power only when
switching because that is when transient gate charging
current flows. POWERSENSE logic requires little space,
and is a good economical solution. The DMOS side of the
process provides a robust user interface to the outside world
on each of the outputs. Peak transient capability of each
output is rated at a maximum of 46 V (typical of an
automotive load dump transient).
resulting in an output resistance (R
less than 1.0
less than 2.0 A of bias current from V
this sleep mode when V
current for the device is 5.0 mA maximum for any
combination of output drivers enabled.
and short to V
load and short to ground are detected when the output is off.
Faults are reported out of the serial output (SO) pin as a new
8–bit word is being fed into the serial input (SI) pin.
microprocessor and the CS1112. The SPI control inputs and
all other logic inputs are compatible with 5.0 V CMOS logic
levels.
The CS1112 was developed for use in very noisy and very
This part uses ON Semiconductor’s POWERSENSE
Power consumption is kept to a minimum using
The CS1112 uses quasi–vertical DMOS transistors
The part can be put in a sleep mode where the part draws
Fault reporting is controlled by the CS1112. Overcurrent
Figure 3 highlights the SPI interface between the
BATT
@ 13 V and 500 mA @ 25 C.
CIRCUIT DESCRIPTION
are detected when the output is on. Open
POWERSENSE
DD
0.5 V. Maximum quiescent
DS(ON)
PWR
) at each output of
. The part enters
combines
APPLICATION INFORMATION
http://onsemi.com
the
CS1112
7
interface are the SI, SO, CSB, and SCLK. The parallel
inputs, which control the outputs can also connect to the
same microprocessor, a separate microprocessor, or any
other sensor or electrical device which meets the voltage
requirements of the CS1112 (V
The four communication lines which define the SPI
SPI communication is as follows (2 scenarios):
Receive Buffer
1.
2.
8–Bit Normal Operation
CSB pin is brought low activating the SPI port. Faults
detected since the last CSB low to high transition are
latched into the serial register when CSB goes low. 8
command bits are clocked into the SI pin. The four
fault bits are clocked out of the SO pin. CSB pin is
brought high translating the final 4 bits to the outputs
turning them on or off. Faults are then detected and
saved in the fault register when CSB goes low.
16–Bit Operation For Command Verify
CSB pin is brought low activating the SPI port. 16 bits
are clocked into the SI pin (the last 4 are the 4 control
pins for the four outputs). CSB pin is brought high
translating the last 4 bits to the outputs turning them
on or off.
CSB pin is brought low activating the SPI port. 16
new bits are clocked into the SI pin. As the new bits
are being clocked in, the first 8 bits being clocked out
of the SO pin are the fault bits, followed by the first
8 bits which were clocked in (the verification bits).
The verification bits should replicate the command
bits.
P
SPI Interface
SCLK
CSB
SO
SI
Figure 3.
X
Shift Register
Output Logic
X
CS1112
X
3 2 1 0
X
3
2 1 0
IN(max)
Fault Reporting
STATUS
IN0
Parallel
Control
IN1
IN2
Inputs
= V
DD
+ 0.3 V).
P