CS1112YDWFR24 ON Semiconductor, CS1112YDWFR24 Datasheet - Page 9

• Manufacturer Part Number: CS1112YDWFR24
• Description: IC DRIVER QUAD PWR OUTPUT 24SOIC
• Manufacturer: ON Semiconductor
• Type: Low Sider

Specifications of CS1112YDWFR24

• Input Type: Non-Inverting
• Number Of Outputs: 4
• On-state Resistance: 1 Ohm
• Current - Output / Channel: 1A
• Current - Peak Output: 6A
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CS1112YDWFR24OSTR

faults and conditions. These include Overvoltage, Current
Limit, Open Circuit, Output Short to Power, Output Short to
Ground, and Flyback Clamp.
Overvoltage
pin. If the voltage on this pin exceeds the Overvoltage
Shutdown Threshold (typically 35 V), all outputs
immediately turn off. The programmed outputs (via serial or
parallel input) turn back on once the voltage is brought back
down below this level.
Current Limit/Short to V
typical) for the Short Circuit/Overcurrent Sense Time
(typically 62.5 s) as it would do during an output short to
V
fault status bit remains latched until the rising edge of CSB.
The output will go into a low duty cycle mode (typically
1.56%) as long as the overcurrent condition exists, and the
channel is on. This protects the integrated circuit from
damaging itself due to its thermal limits.
Open Circuit/Short to Ground
off. A fault bit is set when the Open Load “Off” Detection
Voltage (typically 0.5
“Off” Sense Time (typically 62.5 s) as it would do during
an output short to ground.
Flyback Clamp
protection feature of the CS1112. When driving inductive
loads, it is normal to observe high voltage spikes on the
output pin due to the stored energy in the windings when the
device is turned off. On–chip clamps on the outputs limit the
voltage amplitude on the pin to prevent damage to the
device. Each output has an Output Clamp which limits the
output voltage to 52 V (typical when measured at 20 mA for
100 s).
SI
sent most significant bit first. Data is clocked in on the rising
edge of SCLK. An internal active pull–down is connected to
this input. CMOS logic levels are required on this pin.
SO
input pin of the microprocessor, or it can be daisy–chained
to the serial input (SI) of another SPI compatible device.
This pin is tri–stated unless a low CSB pin selects the device.
BATT
The CS1112 provides protection for a multitude of system
The IC is constantly monitoring the voltage on the V
When the output current exceeds the Overcurrent (4.5 A
Open circuit conditions are detected while the outputs are
While the flyback clamp is not a fault mode, it is a
The SI (Serial Input) receives serial 8–bit or 16–bit words
The SO (Serial Output) can be connected to the serial data
, its fault status bit will be latched to a logic one. The
PIN FUNCTION DESCRIPTION
FAULT MODE OPERATION
V
BATT
DD
) is present for the Open Load
http://onsemi.com
PWR
CS1112
9
The signal on this pin is clocked from the falling edge of the
SCLK pin. The serial output data provides fault information
for each output and returns most significant bit (bit 7) first.
Bits 0 through 3 are output fault bits for outputs 0 through
3, respectively. In 8–bit SPI mode, bits 0–3, under normal
conditions return all zeros representing no faults. A 1
indicates a fault. The output from this pin conforms to
CMOS logic levels.
R
internal current source.
CSB
microprocessor wants to communicate with the CS1112. A
low on this pin enables the SPI communication with the
device and enables the SO pin. After the digital word is
clocked into the IC, a transition from low to high on the CSB
pin translates the last 4 bits of information turning the
outputs on or off. An internal active pull–up is connected to
this input. CMOS logic levels are required on this pin.
SCLK
registers. This pin controls the data being shifted into the SI
pin, and data being shifted out of the SO pin. CMOS logic
levels are required on this pin.
IN0, IN1, IN2, IN3
These are the parallel input pins which may be used to PWM
the outputs. They have 230 mV of hysteresis. These inputs
are OR’d with their corresponding input bit in the serial
control byte. An internal active pull–down is connected to
these pins. CMOS logic levels are required on these pins.
OUT0, OUT1, OUT2, OUT3
have typically 1.0
on these pins has a minimum specification of 3.0 A. A low
duty cycle mode (1.5% typ.) will initiate at a minimum of 1A
and before the current limit.
V
V
STATUS
or overcurrent condition occurs on any of the outputs. This
provides immediate notification to the controller that a fault
is present. The controller can subsequently query the device
(serially) to determine its origin.
PWR
DD
OSC
An 82 k
The CSB (Chip Select Bar) is the select pin when the
The SCLK (Serial Clock) clocks the internal shift
These pins control their corresponding numbered output.
These pins are the output low–side driver pins. They all
14 V Battery voltage input. 5.0 mA (max) is needed.
5.0 V Supply input. 5.0 mA (max) is needed.
Open drain output. This pin goes low when an open load
resistor tied to ground sets up an accurate
R
DS(ON)
at V
PWR
= 13 V. Current limit