A3935KLQ-T Allegro Microsystems Inc, A3935KLQ-T Datasheet - Page 5

• Manufacturer Part Number: A3935KLQ-T
• Description: IC CTRLR MOSFET 3PH 36-SOIC
• Manufacturer: Allegro Microsystems Inc

Specifications of A3935KLQ-T

• Applications: DC Motor Driver, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Load: 7 V ~ 40 V
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 36-QSOP
• Device Type: Full Bridge
• Peak Output Current: 1.6mA
• Output Resistance: 8ohm
• Input Delay: 150ns
• Output Delay: 150ns
• Supply Voltage Range: 4.75V To 5.25V
• Driver Case Style: QSOP
• No. Of Pins: 36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

A3935
Continued on the next page…
ELECTRICAL CHARACTERISTICS (continued)
ENABLE = 22.5 kHz, 50% duty cycle, two phases active;unless otherwise noted
Gate Drives, GLx (internal sink or lower switch stages)
Sink Current (pulsed)
Sink On Resistance
Gate Drives, GHx, GLx (General)
Propagation Delay, Logic only
Output Skew Time
Dead Time (shoot–through prevention)
Sense Amplifier
Input Bias Current
Input Offset Current
Input Resistance
Diff. Input Operating Voltage
Output Offset Voltage
Output Offset Voltage Drift
Input Common Mode Operating Range
Voltage Gain
Low Output Voltage Error
DC Common Mode Attenuation
Output Resistance
Output Dynamic Range
Output Current, Sink
Output Current, Source
VDD Supply Ripple Rejection
VREG Supply Ripple Rejection
Small Signal 3 dB Bandwidth
AC Common Mode Attenuation
Output Slew Rate (positive or negative)
Fault Logic
VDD Undervoltage
VDD Undervoltage Hysteresis
OVSET Operating Voltage Range
OVSET Calibrated Voltage Range
OVSET Input Current Range
VBAT Overvoltage Range
VBAT Overvoltage Hysteresis
Characteristics
2
2
2
2
5,6
3-Phase Power MOSFET Controller for Automotive Applications
PSRR
PSRR
V
∆V
Symbol
∆V
V
V
V
r
BW
A
V
SET(ov)cal
I
I
DSL(on)
ΔV
SET(ov)
SET(ov)
t
t
CSOUT
source
BAT(ov)
V
A
I
DD(uv)
I
VC(ac)
sk(o)
dead
V
V
SR
BAT(ov)
A
E
I
t
bias
I
sink
DD(uv)
r
pd
xL
IO
r
OO
VC
O
ID
IC
i
OO
V
V
f3db
VREG
VDD
6
V
V
I
I
Logic input to unloaded GHx, GLx
Grouped by edge, phase–to–phase
Between GHx, GLx transitions of same phase
CSP = CSN = 0 V
CSP = CSN = 0 V
CSP with respect to GND
CSN with respect to GND
V
CSP = CSN = 0 V
CSP = CSN = 0 V
CSP = CSN
V
V
CSP = CSN = 200 mV
V
I
V
V
CSP = CSN = GND, frequency = 0 to 1 MHz
CSP = CSN = GND, frequency = 0 to 300 kHz
10 mV input
V
200 mV step input, measured at 10/90% points
Decreasing V
V
0 V < V
Increasing V
Percent of V
xL
xL
CSOUT
at T
CSOUT
CSOUT
CSOUT
DSL
DSL
ID
ID
ID
cm
DD(recovery)
= 150 mA, T
= 150 mA, T
= CSP – CSN, –1.3V < CSP,N < 4V
= 40 to 200 mV
= 0 to 40 mV, V
= 250 mV(pp), frequency = 0 to 800 kHz
= 10 V, T
= 10 V, T
J
= –100 μA at top rail, 100 μA at bottom rail
SET(ov)
= –40°C to 150°C, V
= 2.0 V
= 2.5 V
= 2.5 V
– V
BAT(ov)
BAT
DD
J
< 2.5 V
J
J
J
= 25°C
DD(uv)
, V
= 135°C
= 25°C
= 135°C
SET(ov)
value set by V
O
= (19.2 × V
Conditions
= 0 V
BAT
ID
SET(ov)
) + V
= 7 to 16 V, V
O
+ E
v
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
DD
= 4.75 to 5.25 V,
0.075
–180
Min.
–1.5
18.6
–1.0
–1.0
19.4
19.4
550
100
1.8
3.0
3.8
9.0
75
77
28
20
20
45
26
10
–
–
–
–
–
–
–
–
–
–
–
0
0
Typ
19.2
22.4
850
250
100
4.0
8.0
1.6
80
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
. Max.
V
–360
±200
19.8
0.25
25.4
150
180
±35
450
±25
300
V
6.0
7.5
4.0
4.3
2.5
1.0
50
DD
40
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DD
–
μV/°C
Units
MHz
V/μs
V/V
mA
mA
mV
mV
mV
mA
mA
mV
kΩ
kΩ
μA
μA
dB
dB
dB
dB
μA
ns
ns
ns
%
Ω
Ω
V
Ω
V
V
V
V
V
V
5