A3938SLD Allegro Microsystems Inc, A3938SLD Datasheet - Page 6

• Manufacturer Part Number: A3938SLD
• Description: IC CTRLR MOSFET 3PH 38-TSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A3938SLD

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Supply: 18 V ~ 50 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Voltage - Load: -

A3938
RESET.
50 kΩ pull-up to LCAP. Setting RESET to 1 coasts or brakes
the motor, depending on the state of the BRKSEL pin. Set-
ting RESET to 0 enables the gate drive to follow commuta-
tion logic. Setting RESET to 1 overrides the BRAKE pin.
GLA/GLB/GLC.
MOSFET drivers. External series gate resistors can be used
to control slew rate seen at the power driver gate, thereby
controlling the di/dt and dv/dt of Sx outputs.
SA/SB/SC.
these pins sense the voltages switched across the load. The
pins are also connected to the negative side of the bootstrap
capacitors and the negative supply connections for the fl oat-
ing high-side drivers.
GHA/GHB/GHC.
N-channel MOSFET drivers. External series gate resistors
can be used to control slew rate seen at the power driver
gate, thereby controlling the di/dt and dv/dt of Sx outputs.
CA/CB/CC.
tors, providing positive supply for high-side gate drivers. The
bootstrap capacitors are charged to approximately VREG
when the output Sx terminals go low. When the outputs
swing high, the voltages on these pins rise with the outputs to
provide the boosted gate voltages needed for the N-channel
power MOSFETs.
MODE. Logic input to set current-decay mode. In response
to a PWM Off command, Slow Decay mode (MODE = 1)
switches off the high-side FET, and Fast Decay mode
(MODE = 0) switches off the high-side and low-side FETs.
Has an internal 50 kΩ pull-up to LCAP.
H1/H2/H3.
to LCAP. Confi gured for 120-degree electrical spacing.
DIR.
tation Truth Table, on the next page). Has internal, 50 kΩ
pull-up to LCAP.
FAULT.
be pulled high (usually by 5.1 kΩ external pull-up) for any of
the following fault conditions:
• Invalid Hall sensor input code (coasts the motor).
• Undervoltage condition detected at VREG (coasts or brakes
Logic input to reverse rotation (see the table Commu-
Open-drain output to indicate fault condition. Will
A logic input that enables the device. Has internal
Hall sensor inputs with internal, 50 kΩ pull-ups
Directly connected to the motor terminals,
High-side connections for bootstrap capaci-
Low-side gate drive outputs for external
High-side gate drive outputs for
Three-Phase Power MOSFET Controller
Pin Descriptions
• Thermal shutdown (coasts the motor).
• Motor lead (SA/SB/SC) connected to ground (turns off
Only the “short-to-ground” fault is latched, but it is cleared
at each commutation. If the motor has stalled due to a short-
to-ground being detected, toggling the RESET pin or repeat-
ing a power-up sequence clears the fault.
BRAKE.
to 1 turns on low-side MOSFETs, and turns off the high-side
MOSFETs. This effectively shorts the BEMF in the windings
and brakes the motor. Internal 50 kΩ pull-up to LCAP. Set-
ting RESET to 1 overrides this BRAKE pin. See also BRKSEL.
BRKCAP.
capacitor used to provide the positive power supply for the
sink drive outputs for a power-down condition. This allows
predictable braking, if desired. Using a 4.7 F capacitor will
provide 6.5 V gate drive for 300 ms. If the power-down brak-
ing option is not needed (i.e., BRKSEL = 0), then this pin
should be tied to VREG.
BRKSEL
power-down condition or RESET = 1. Internal 50 kΩ pull-up
to LCAP. Setting BRKSEL to 0 enables Coast mode. Setting
BRKSEL to 1 enables Brake mode.
PWM.
MOSFETs selected by Hall input logic. Setting PWM to 0
turns off the selected MOSFETs. Keep the PWM input held
high to utilize internal current control circuitry. Internal
50 kΩ pull-up to LCAP.
RC.
fi xed off-time. C
Application Information). It is recommended that the fi xed
off-time should not be less than 10 μs. The resistor should be
in the range between 10 kΩ and 500 kΩ.
VREG.
and the bootstrap capacitor charge circuit. As a regulator, use
a 10 μF decoupling/storage capacitor (ESR < 1 Ω) from this
pin to AGND, as close to the device pins as possible.
Note: For 12 V applications, the VREG pin should be
shorted to VBB.
only the high-side power MOSFETs).
the motor depending on stored setting for BRKSEL).
Analog input. Connection for R
Speed control input. Setting PWM to 1 turns on
Regulated 13 V supply for the low-side gate drive
Logic input for braking function. Setting BRAKE
. Logic input to enable/disable braking upon
This pin is for connection of the reservoir
T
also sets the BLANK time (see the section
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
T
and C
T
to set the
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