A8904SLP Allegro Microsystems Inc, A8904SLP Datasheet - Page 18
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A8904SLP
Manufacturer Part Number
A8904SLP
Description
IC CTRLR/DRVR DC MOTOR 28TSSOP
Manufacturer
Allegro Microsystems Inc
Datasheet
1.A8904SLPTR-T.pdf
(19 pages)
Specifications of A8904SLP
Applications
DC Motor Driver, Brushless (BLDC), 3 Phase
Number Of Outputs
1
Current - Output
±1.4A
Voltage - Load
4 V ~ 14 V
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A8904SLPT
Manufacturer:
ALLEGRO/雅丽高
Quantity:
20 000
Company:
Part Number:
A8904SLPTR-T
Manufacturer:
Allegro
Quantity:
482
28X
A8904
24X
0.10
0.10
0.41 ±0.10
0.25
C
+0.05
–0.06
C
28
1
24
1
A
2
For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
2
B
9.70 ±0.10
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
15.40±0.20
5.00
1.27
0.65
3-Phase Brushless DC Motor Controller/Driver
LB package, 24-pin SOICW
LP package, 28-pin TSSOP
with exposed thermal pad
3.00
7.50±0.10
0.20 ±0.10
0.10 MAX
4.40 ±0.10
SEATING
PLANE
2.65 MAX
1.20 MAX
SEATING
PLANE
10.30±0.33
6.40 ±0.20
C
C
A Terminal #1 mark area
B
C
Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Exposed thermal pad (bottom surface)
A Terminal #1 mark area
B
Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
GAUGE PLANE
GAUGE PLANE
4° ±4
0.25
0.84
SEATING PLANE
0.25
0.27
4° ±4
SEATING PLANE
0.60 ±0.15
0.15
+0.44
–0.43
(1.00)
+0.07
–0.06
+0.05
–0.06
with Back EMF Sensing
1.65
2.20
28
1
24
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
1
2
0.45
2
B
C
PCB Layout Reference View
PCB Layout Reference View
5.00
0.65
0.65
3.00
1.27
9.60
6.10
17