A3936SEDTR-T Allegro Microsystems Inc, A3936SEDTR-T Datasheet - Page 9

IC MOTOR DRIVER PWM 3PH 44-PLCC

A3936SEDTR-T

Manufacturer Part Number
A3936SEDTR-T
Description
IC MOTOR DRIVER PWM 3PH 44-PLCC
Manufacturer
Allegro Microsystems Inc
Datasheet

Specifications of A3936SEDTR-T

Applications
DC Motor Driver, Brushless (BLDC), 3 Phase
Number Of Outputs
1
Current - Output
±3A
Voltage - Load
9 V ~ 50 V
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Operating Current
10mA
Operating Temperature Classification
Commercial
Package Type
PLCC
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
620-1129-2
A3936SEDTR-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3936SEDTR-T
Manufacturer:
STANSON
Quantity:
12 000
Part Number:
A3936SEDTR-T
Manufacturer:
Allegro MicroSystems, LLC
Quantity:
10 000
A3936
Terminal List
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
BRAKE
SENSE
Pin Name
GND
GND
HA+
HA-
HB+
HB-
HC+
HC-
V
REF
GND
GND
GND
BRAKE
SENSE
SR
OUTA
HBIAS
VBB1
LSS1
OUTB
GND
GND
GND
LSS2
VBB2
TACH
OUTC
V
CP1
CP2
SLEEP
GND
GND
GND
OSC
V
DIR
ENABLE
EXTMODE
BLANK
PFD2
PFD1
GND
OUTA
GND
GND
GND
DD
CP
REG
VDD
HC+
REF
HC-
SR
10
11
12
13
14
15
16
17
7
8
9
DMOS Three-Phase PWM Motor Driver
Pin-out Diagram
Pin Description
Hall input
Hall input
Hall input
Hall input
Hall input
Hall input
Logic Supply Voltage
G
Logic Input
Sense Resistor Connection
Logic Input (Disabled = Low, Active SR = High)
DMOS H – Bridge A
Connection for hall element neg side
Load Supply Voltage
Low Side Source connection
DMOS H – Bridge B
Low Side Source connection
Load Supply Voltage
Speed output
DMOS H – Bridge C
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Logic input for SLEEP mode
Oscillator Terminal
Regulator decoupling Terminal
Logic Input
Logic Input
Logic Input
Logic Input
Logic Input
Logic Input
Power Ground Tab
m
Reference Input Voltage
39
38
37
36
35
34
33
32
31
30
29
ENABLE
DIR
VREG
OSC
GND
GND
GND
SLEEP
CP2
CP1
VCP
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
9

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