NCP1605ADR2G ON Semiconductor, NCP1605ADR2G Datasheet - Page 20

• Manufacturer Part Number: NCP1605ADR2G
• Description: IC PFC CONTROLLER CCM/DCM 16SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1605ADR2G

• Mode: Continuous Conduction (CCM), Discontinuous Conduction (DCM)
• Frequency - Switching: 250kHz
• Current - Startup: 12mA
• Voltage - Supply: 10 V ~ 20 V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Switching Frequency: 250 KHz
• Maximum Power Dissipation: 550 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Regulation Block and Low Output Voltage Detection
inverting input and output is provided. It features a typical
transconductance gain of 200 mS and a maximum
capability of ±20 mA. The output voltage of the PFC stage
is typically scaled down by a resistors divider and
monitored by the inverting input (feedback pin − Pin 4).
The bias current is minimized (less than 500 nA) to allow
the use of a high impedance feedback network. The output
of the error amplifier is pinned out for external loop
compensation (Pin 3). Typically a capacitor in the range of
100 nF, is applied between Pin 3 and ground, to set the
regulation bandwidth below 20 Hz, as need in PFC
applications.
variations of the load, may result in excessive over and
undershoots. Overshoots are limited by the Overvoltage
Protection (see OVP section). To contain the undershoots, an
internal comparator monitors the feedback (V
V
V
Figure 57. Input Voltage and On−time vs Time (example with F
control
Pin4
A transconductance error amplifier with access to the
Provided the low bandwidth of the regulation loop, sharp
350,00
300,00
250,00
200,00
150,00
100,00
FB
50,00
0,00
is lower than 95.5% of its nominal value, it connects a
0
0.955*Vref
Figure 58. Regulation Block
OFF
OVLflag1
V
ref
V
2
Detect
out
Low
+
+
-
-
3 V
Amplifier
Error
4
pfcOK
±20 mA
+
2R
V
R
F
V
REGUL
6
Pin4
200 mA
) and when
http://onsemi.com
8
+
V
F
time (ms)
20
10
an accurate range:
•
•
offset down by (V
to the “V
Finally, the output of the regulation is a signal (“V
of the block diagram) that varies between 0 and 1 V.
200 mA current source to speed−up the charge of the
compensation capacitor (Cpin3). Finally, it is like if the
comparator multiplied the error amplifier gain by 10.
is not enabled during the startup sequence of the PFC stage
but only once the converter has stabilized (that is when the
V
The swing of the error amplifier output is limited within
Hence, V
One must note that this circuitry for undershoots limitation,
It is forced above a voltage drop (V
It is clamped not to exceed 3.0 V + the same V
drop.
REGUL
SW
= 100 kHz, Pin =150 W, V
Figure 59. Correspondence between V
12
TON
0 V
Pin3
processing block” and the PWM section.
V
features a 3 V voltage swing. V
F
F
1 V
) and divided by three before it connects
14
and V
16
REGUL
AC
3 V + V
= 230 V, L = 200 mH)
F
) by some circuitry.
18
F
V
CONTROL
Pin3
CONTROL
F
voltage
REGUL
20
is then
3,50
3,00
2,50
2,00
1,50
1,00
0,50
0,00
”