ISL6537CRZ Intersil, ISL6537CRZ Datasheet
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ISL6537CRZ
Specifications of ISL6537CRZ
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ISL6537CRZ Summary of contents
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... Over Temperature PART TEMP. MARKING RANGE (°C) PACKAGE ISL6537CR 6x6 QFN L28.6x6 ISL6537CRZ 6x6 QFN (Pb-free) | Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved DDQ TT PKG. DWG. # ...
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Block Diagram VDDQ P12V R GU EA4 DRIVE4 GMCH DUAL LDO R GL FB4 REFADJ4 P12V EA3 DRIVE3 FB3 P12V EA2 DRIVE2 FB2 5VSBY P12V S3# S5# FB POR MONITOR AND CONTROL FAULT SOFT-START & ENABLE A SOFT-START & ENABLE ...
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Simplified Power System Diagram V DDQ SLP_S3 SLP_S5 GMCH + Q5 V TT_GMCH/CPU + Typical Application V DDQ_DDR SLP_S5 SLP_S3 GMCH TT_GMCH/CPU 3 ISL6537 12V 5VSBY SLEEP STATE LOGIC PWM ...
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... Thermal Information Thermal Resistance QFN Package (Notes Maximum Junction Temperature (Plastic Package +150° 7.0V (DC) Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp SYMBOL TEST CONDITIONS I S3# and S5# HIGH, UGATE/LGATE Open CC_S0 I S5# LOW, S3# Don’t Care, UGATE/LGATE ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics (Continued) PARAMETER PWM CONTROLLER GATE DRIVERS UGATE and LGATE Source UGATE and LGATE Sink VTT REGULATOR Upper Divider Impedance Lower ...
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Functional Pin Description 5VSBY (Pin 1) 5VSBY is the bias supply of the ISL6537 typically connected to the 5V standby rail of an ATX power supply. During S4/S5 sleep states the ISL6537 enters a reduced power mode and ...
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BOOT (Pin 25) This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-channel MOSFET. FB2 (Pin 11) Connect the output of the V ...
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SLP_S3# SLP_S5# 12V POR 12V 0V V DDQ_DDR 0V V DDQ_DDR V TT_DDR 0V V GMCH_UPPER 0V V GMCH 0V V TT_GMCH/CPU 0V VIDPGD (3 SOFTSTART CYCLES Soft-Start Rise Time Dependent ...
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The digital soft-start for the PWM regulator is accomplished by clamping the error amplifier reference input to a level proportional to the internal digital soft-start voltage. As the soft- start voltage slews up, the PWM comparator generates PHASE pulses of ...
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Fault Counter reaches a count any other time. The 16384 counts that are required to reset the Fault Reset Counter represent 8 soft-start cycles, as one soft-start cycle is 2048 clock ...
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Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit ...
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DRIVER OSC PWM COMPARATOR - DRIVER ΔV + OSC E REFERENCE ERROR AMP DETAILED COMPENSATION COMPONENTS COMP ISL6537 REFERENCE ⎛ ⎞ ...
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The output voltage programming resistor will depend on the value chosen for the feedback resistor and the desired output voltage of the particular regulator. × ---------------------------------- - V 0.8V – DDQ × ...
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Place the small ceramic capacitors physically close to the MOSFETs and between the drain of upper MOSFET and the source of lower MOSFET. The important parameters for the bulk input capacitance are the voltage rating and the RMS ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...