ISL97522IRZ-T Intersil, ISL97522IRZ-T Datasheet - Page 8

• Manufacturer Part Number: ISL97522IRZ-T
• Description: IC SUPPLY CTRL 4CH TFT-LCD 38QFN
• Manufacturer: Intersil

Specifications of ISL97522IRZ-T

• Applications: LCD TV/Monitor
• Current - Supply: 3mA
• Voltage - Supply: 4.5 V ~ 13.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
PIN #
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
26
27
28
29
30
31
32
33
34
35
36
37
38
1
2
3
4
5
6
7
8
9
PIN NAME
ISADJB
PGNDB
PGNDP
ACGND
ILADJB
ISADJL
ILADJL
CINTB
DRVN
CINTL
VDCP
DELB
VCC1
DRVB
ISINB
DRVL
DRVP
VREF
CDLY
VHIB
COM
FBW
VHIL
DRN
VDC
SRC
FBB
FBP
CC2
CTL
ENL
FBL
VIN
NC
NC
NC
EN
LX
Negative LDO base drive; open drain of an internal P-Channel MOSFET.
Active low control output for optional delay control for external A
goes to high.
Negative LDO voltage feedback input pin; regulates to 0.2V nominal.
Supply input, connect to V
A
Current feedback adjust for A
With a resistor connected from this pin to GND sets the current limit of the external N-channel FET for A
A
Gate driver output for the external N-Channel switch.
Power GND for A
Internal Drive of Boost controller, Connect to VDCP.
Sense the drain voltage of the external N-channel FET and connected to the internal current limit comparator.
Main supply input.
Enable pin; high enable, low disabled.
V
V
Gate driver output for external N-channel switch.
Power GND.
V
With resistor connected from this pin to GND sets the current limit of the external N-channel FET.
V
Current feedback adjust for V
Positive supply for all internal analog circuits.
Positive supply for external N-Channel FET gate drives.
Positive LDO base drive; open drain of an internal N-Channel MOSFET.
Low noise signal ground.
Bandgap voltage bypass terminal; bypass with a 0.1µF to analog GND; can be used as charge pump reference.
Positive LDO voltage feedback input pin; regulates to 1.2V nominal.
Supply input, connect to V
With a capacitor connect from this pin to GND, sets the delay time for start-up sequence and fault detection timeout.
Input control for switch output.
Enable pin for V
Lower reference voltage for switch output.
Switch output; when CTL = 1, COM is connected to SRC through a 15Ω resistor, when CT: = 0, COM is connected
to DRN through a 30Ω resistor.
Upper reference voltage for switch output.
VDD
VDD
LOGIC
LOGIC
LOGIC
LOGIC
8
regulator voltage feedback input pin; regulates to 1.2V nominal.
integrator output, connect 2.2nF to analog GND.
boost strap mode.
switch connection.
regulator voltage feedback pin; regulates to 1.2V nominal.
integrator output, connect 2.2nF to analog GND.
LOGIC
VDD
.
high enable; low disabled.
IN
IN
.
.
VDD
LOGIC
.
ISL97522
.
PIN DESCRIPTION
VDD
P-Channel FET; when fault is detected, this pin
December 13, 2006
VDD.
FN7445.0