MAX17000AETG+ Maxim Integrated Products, MAX17000AETG+ Datasheet - Page 12

• Manufacturer Part Number: MAX17000AETG+
• Description: IC PWM CTLR DDR/DDR2/DDR3 24TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17000AETG+

• Applications: Memory, DDR2/DDR3 Regulator
• Current - Supply: 2mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Complete DDR2 and DDR3 Memory
Power-Management Solution
12
PIN
______________________________________________________________________________________
10
11
12
13
1
2
3
4
5
6
7
8
9
PGOOD1
PGOOD2
PGND2
STDBY
NAME
REFIN
VTTR
VTTS
VTTI
CSH
OVP
CSL
VTT
FB
OVP Mode Control. This input selectively enables/disables the SMPS OV protection feature and
output discharge mode. When enabled, the SMPS OV protection feature is enabled. Connect OVP to
the following voltage levels for the desired function:
High (> 2.4V) = Enable SMPS OV protection, and SMPS and VTT discharge FETs.
Low (AGND) = Disable SMPS OV protection, and SMPS and VTT discharge FETs.
Open-Drain Power-Good Output. PGOOD1 is low when the SMPS output voltage is more than 15%
(typ) beyond the normal regulation point, during soft-start, and in shutdown.
After the soft-start circuit has terminated, PGOOD1 becomes high impedance if the SMPS output is
in regulation.
Open-Drain Power-Good Output. PGOOD2 is low when the VTT output voltage is more than 10%
(typ) beyond the normal regulation point, in shutdown, in standby, and during soft-start.
After the SMPS soft-start circuit has terminated, PGOOD2 becomes high impedance if the VTT
output is in regulation.
Standby Control Input. When SHDN is high and STDBY is low, the MAX17000 enters a low-
quiescent current mode, putting the SMPS in ultra-skip operation and turning off the VTT output
(high-Z). This mode helps save converter power loss in computer standby operation.
When STDBY is high, normal SMPS operation resumes and the VTT output is enabled.
Sense Pin for Termination Supply Output. Normally connected to the VTT pin to allow accurate
regulation to V
Termination Reference Buffer Output. VTTR tracks V
tracks V
0.33µF ceramic capacitor.
Power Ground for VTT. Connect PGND2 externally to the underside of the exposed pad.
Termination Power-Supply Output. Connect VTT to VTTS to regulate the VTT voltage to the VTTS
regulation setting.
Termination Power-Supply Input. VTTI is the input power supply to the VTT linear regulator.
Normally connected to the output of the SMPS regulator for DDR applications.
External Reference Input. REFIN sets the feedback regulation voltage (VTTR = VTTS = V
the MAX17000.
Connect REFIN to V
Connect a 0.5V to 1.5V voltage input to set the adjustable output for VTT, VTTS, and VTTR.
Feedback Input for SMPS Output. Connect to V
+1.5V output. For an adjustable output (1.0V to 2.7V), connect FB to a resistive divider from the
output voltage. FB regulates to +1.0V.
Negative Input of the PWM Output Current-Sense and Supply Input for VTTR. Connect CSL to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
CSL is also the path for the internal 16
enabled.
Positive Input of the PWM Output Current Sense. Connect CSH to the positive side of the output
current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing.
REFIN
when a voltage between 0.5V to 1.5V is set at REFIN. Decouple VTTR to AGND with a
CSL
/2 or the REFIN voltage.
CC
to use the internal V
discharge MOSFET when V
CSL
FUNCTION
CC
/2 divider.
for a fixed +1.8V output or to AGND for a fixed
CSL
/2 when REFIN is connected to V
CC
UVLO occurs with OVP
Pin Description
CC
REFIN
. VTTR
) of