MAX8660ETL+T Maxim Integrated Products, MAX8660ETL+T Datasheet - Page 36

• Manufacturer Part Number: MAX8660ETL+T
• Description: IC POWER MANAGE XSCALE 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8660ETL+T

• Applications: Processor
• Voltage - Supply: 2.6 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

High-Efficiency, Low-I
Voltage Management for Mobile Applications
The MAX8660/MAX8661 are write-only devices and
recognize the “write byte” protocol as defined in the
SMBus specification and shown in section A of Figure
11. The “write byte” protocol allows the I
device to send 1 byte of data to the slave device. The
“write byte” protocol requires a register pointer address
for the subsequent write. The MAX8660/MAX8661
acknowledge any register pointer even though only a
subset of those registers actually exists in the device.
The “write byte” protocol is as follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
3) The addressed slave asserts an acknowledge by
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) The master sends a STOP condition.
36
Table 10. DVM Voltage-Change Register (VCC1, 0x20)
REGISTER
ADDRESS
by a write bit.
pulling SDA low.
______________________________________________________________________________________
0x20
REGISTER
NAME
VCC1
BIT
I
7
6
5
4
3
2
1
0
2
C Write Operation
NAME
MGO
SGO
AGO
MVS
SVS
AVS
R
R
2
C master
Q
V5 (VCC_MVT) voltage select:
0—Ramp V5 to voltage selected by MDTV1 (default)
1—Ramp V5 to voltage selected by MDTV2
Start V5 (VCC_MVT) voltage change:
0—Hold V5 at current level (default)
1—Ramp V5 as selected by MVS
V4 (VCC_SRAM) voltage select:
0—Ramp V4 to voltage selected by SDTV1 (default)
1—Ramp V4 to voltage selected by SDTV2
Start V4 (VCC_SRAM) voltage change:
0—Hold V4 at current level (default)
1—Ramp V4 as selected by SVS
Reserved
Reserved
V3 (VCC_APPS) voltage select:
0—Ramp V3 to voltage selected by ADTV1 (default)
1—Ramp V3 to voltage selected by ADTV2
Start V3 (VCC_APPS) voltage change:
0—Hold V3 at current level (default)
1—Ramp V3 as selected by AVS
, PMICs with Dynamic
In addition to the write-byte protocol, the MAX8660/
MAX8661 recognize the multiple byte register-data pair
protocol as shown in section B of Figure 11. This proto-
col allows the I
only once and then send data to multiple registers in a
random order. Registers may be written continuously
until the master issues a STOP condition.
The multiple-byte register-data pair protocol is as
follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
3) The addressed slave asserts an acknowledge by
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) Steps 5 to 7 are repeated as many times as
10)The master sends a STOP condition.
by a write bit.
pulling SDA low.
the master requires. Registers may be accessed in
random order.
2
C master device to address the slave
FUNCTION