LM75BIMMX-3+ Maxim Integrated Products, LM75BIMMX-3+ Datasheet - Page 9

• Manufacturer Part Number: LM75BIMMX-3+
• Description: IC TEMP SENSOR WATCHDOG 8MSOP
• Manufacturer: Maxim Integrated Products

Specifications of LM75BIMMX-3+

• Function: Temp Sensor, Watchdog
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -55°C ~ 125°C
• Output Type: I²C™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Temperature data is stored in the Temperature, T
Point, and T
data format is 9 bits, two’s complement, and the register
is read out in 2 bytes: an upper byte and a lower byte.
Bits D15–D7 contain the temperature data, with the LSB
representing 0.5°C and the MSB representing the sign
bit (see Table 3). The MSB is transmitted first. The last 7
bits of the lower byte, bits D6–D0, are don’t cares.
Set bit D0 in the Configuration register to 1 to place the
LM75 in shutdown mode and reduce supply current to
4µA. In interrupt mode, entering shutdown resets the
OS output. While in shutdown, the I
and T
Configuration register remain accessible to the master.
The fault queue prevents OS false tripping in noisy
environments. The number of faults set in the queue (up
to 6) must occur to trip the OS output.
The events that trigger OS are identical between com-
parator and interrupt modes. In comparator mode, OS
is asserted when the temperature rises above the T
value. OS is deasserted when the temperature drops
below the T
ed when the temperature rises above the T
falls below the T
performing a read operation.
The OS output is an open-drain output without an inter-
nal pullup. Connect a pullup resistor from OS to +V
Using larger resistance values reduces any tempera-
ture errors due to self heating from current entering OS.
The OS polarity can be programmed for active-low or
active-high operation. In active-low operation, OS goes
low when triggered by a temperature event.
The LM75’s Pointer register selects between four data
registers (see Figure 6). At power-up, the pointer is set
to read the Temperature register at address 0x00. The
Pointer register latches the last location to which it was
set. All registers are read and write, except the
Temperature register, which is read only.
Write to the Configuration register by writing an address
byte, a data pointer byte, and a data byte. If 2 data
SMBus is a trademark of Intel Corp.
OS
and T
HYST
HYST
HYST
HYST
value. In interrupt mode, OS is assert-
Digital Temperature Sensor and Thermal
_______________________________________________________________________________________
Set Point registers. The temperature
Comparator/Interrupt Mode
value. OS is deasserted only after
Temperature Data Format
limit registers along with the
Internal Registers
2
C remains active
Watchdog with 2-Wire Interface
Fault Queue
OS Polarity
OS Output
Shutdown
OS
value or
OS
Set
OS
S
.
bytes are written, the second data byte overrides the
first. The T
byte, 1 pointer byte, and 2 data bytes. If only 1 data
byte is written, it is saved in bits D15–D8 of the respec-
tive register. If more than 2 data bytes are written, only
the first 2 bytes are recognized while the remaining
bytes are ignored.
Read from the LM75 in one of two ways. If the location
latched in the Pointer register is set from the previous
read, the new read consists of an address byte, fol-
lowed by retrieving the corresponding number of data
bytes. If the Pointer register needs to be set to a new
address, perform a read operation by writing an
address byte, pointer byte, repeat start, and another
address byte.
An inadvertent 8-bit read from a 16-bit register, with the
D7 bit low, can cause the device to stop in a state
where the SDA line is held low. Ordinarily, this would
prevent any further bus communication until the master
sends nine additional clock cycles or SDA goes high.
At that time, a stop condition resets the device. If the
additional clock cycles are not generated by the mas-
ter, the LM75 bus resets and unlocks after the bus time-
out period has elapsed.
Figure 6. Block Diagram
A2/RESET
SCL
A0
A1
SDA
OS
POINTER = 0000 0000
POINTER = 0000 0011
TEMPERATURE
T
(READ/WRITE)
(READ ONLY)
OS
and T
SET POINT
DATA
+V
S
FOR COMMUNICATION)
HYST
(SELECTS REGISTER
POINTER REGISTER
INTERFACE
SMBus™
BLOCK
GND
registers require 1 address
REGISTER SELECT
ADDRESS
POINTER = 0000 0001
POINTER = 0000 0010
T
CONFIGURATION
HYST
(READ/WRITE)
(READ/WRITE)
SET POINT
LM75
OS
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