ADM1027ARQ-REEL ON Semiconductor, ADM1027ARQ-REEL Datasheet - Page 10
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ADM1027ARQ-REEL
Manufacturer Part Number
ADM1027ARQ-REEL
Description
IC REMOTE THERMAL CTRLR 24-QSOP
Manufacturer
ON Semiconductor
Series
dBCool®r
Datasheet
1.ADM1027ARQ.pdf
(56 pages)
Specifications of ADM1027ARQ-REEL
Rohs Status
RoHS non-compliant
Function
Fan Control, Temp Monitor
Topology
ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
Sensor Type
External & Internal
Sensing Temperature
0°C ~ 105°C, External Sensor
Output Type
SMBus™
Output Alarm
No
Output Fan
Yes
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
0°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
24-QSOP
ADM1027
Notes
1. It is possible to read a data byte from a data register without
2. In Figures 6 to 8, the serial bus address is shown as the default
3. In addition to supporting the send byte and receive byte
4. If it is required to perform several read or write operations in
ADM1027 WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADM1027 are discussed below. The following abbreviations are
used in the diagrams:
S – START
P – STOP
R – READ
W – WRITE
A – ACKNOWLEDGE
A – NO ACKNOWLEDGE
The ADM1027 uses the following SMBus write protocols:
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
For the ADM1027, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 9.
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start con-
dition immediately after the final ACK and carry out a single
byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
Figure 9. Setting a Register Address for Subsequent Read
first writing to the address pointer register if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register, because the first data byte of a write
is always written to the address pointer register.
value 01011(A1)(A0), where A1 and A0 are set by the address
select mode function previously defined.
protocols, the ADM1027 also supports the read byte protocol
(see System Management Bus specifications Rev. 2.0 for
more information).
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.
write bit (low).
transaction ends.
write bit (low).
1
S
ADDRESS
SLAVE
2
W A
3
REGISTER
ADDRESS
4
5
A P
6
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3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
This is illustrated in Figure 10.
ADM1027 READ OPERATIONS
The ADM1027 uses the following SMBus read protocols:
Receive Byte
This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the trans-
In the ADM1027, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
Alert Response Address
Alert Response Address (ARA) is a feature of SMBus devices,
which allows an interrupting device to identify itself to the host
when multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the alert response
3. The device whose SMBALERT output is low responds to
4. If more than one device’s SMBALERT output is low, the one
transaction.
read bit (high).
action ends.
address (ARA = 0001 100). This is a general call address that
must not be used as a specific device address.
the alert response address, and the master reads its device
address. The address of the device is now known and it can
be interrogated in the usual way.
with the lowest device address will have priority, in accordance
with normal SMBus arbitration.
Figure 11. Single Byte Read from a Register
Figure 10. Single Byte Write to a Register
1
S
ADDRESS
SLAVE
2
1
S
ADDRESS
SLAVE
W A
2
3
REGISTER
ADDRESS
R A DATA A P
3
4
4
5
A DATA A P
5
6
6
7 8
REV. A