ADM1027ARQ-REEL ON Semiconductor, ADM1027ARQ-REEL Datasheet - Page 43
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ADM1027ARQ-REEL
Manufacturer Part Number
ADM1027ARQ-REEL
Description
IC REMOTE THERMAL CTRLR 24-QSOP
Manufacturer
ON Semiconductor
Series
dBCool®r
Datasheet
1.ADM1027ARQ.pdf
(56 pages)
Specifications of ADM1027ARQ-REEL
Rohs Status
RoHS non-compliant
Function
Fan Control, Temp Monitor
Topology
ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
Sensor Type
External & Internal
Sensing Temperature
0°C ~ 105°C, External Sensor
Output Type
SMBus™
Output Alarm
No
Output Fan
Yes
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
0°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
24-QSOP
Register Address
0x30
0x31
0x32
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADM1027
reports the PWM duty cycles back through these registers. The PWM duty cycle values will vary according to temperature in
automatic fan speed control mode. During fan startup, these registers report back 0x00. In software mode, the PWM duty cycle
outputs can be set to any duty cycle value by writing to these registers.
Bit
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
REV. A
Name
STRT
LOCK
RDY
FSPD
V
FSPDIS
TODIS
V
CC
¥
I
Table IX. Register 0x40 – Configuration Register 1 (Power-On Default = 0x00)
R/W
Read/Write
Read/Write
Read/Write
R/W
Read/Write
Write Once
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Table VIII. Current PWM Duty Cycle Registers (Power-On Default = 0xFF)
Description
PWM1 Current Duty Cycle (0% to 100% duty cycle = 0x00 to 0xFF)
PWM2 Current Duty Cycle (0% to 100% duty cycle = 0x00 to 0xFF)
PWM3 Current Duty Cycle (0% to 100% duty cycle = 0x00 to 0xFF)
Description
Logic 1 enables monitoring and PWM control outputs based on the limit settings pro-
grammed. Logic 0 disables monitoring and PWM control based on the default power-up
limit settings. Note that the limit values programmed are preserved even if a LOGIC 0 is
written to this bit and the default settings are enabled. This bit becomes read-only and
cannot be changed once Bit 1 (lock bit) has been written. All limit registers should be
programmed by BIOS before setting this bit to 1 (lockable).
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable
registers become read-only and cannot be modified until the ADM1027 is powered down
and powered up again. This prevents rogue programs such as viruses from modifying
critical system limit settings (lockable).
This bit gets set to 1 by the ADM1027 to indicate that the device is fully powered up
and ready to begin systems monitoring.
When set to 1, this runs all fans at full speed. Power-on default = 0. This bit does not get
locked at any time.
BIOS should set this bit to 1 when the ADM1027 is configured to measure current
from an ADI ADOPT
allow monitoring software to display CPU watts usage (lockable).
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs will go
high for the entire fan spin-up timeout selected.
When this bit is set to 1, the SMBus timeout feature is disabled. This allows the ADM1027
to be used with SMBus controllers that cannot handle SMBus timeouts (lockable).
When this bit is set to 1, the ADM1027 rescales its V
If this bit is 0, the ADM1027 measures V
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®
VRM controller and measure the CPU’s core voltage. This will
CC
as a 3.3 V supply (lockable).
CC
pin to measure a 5 V supply.
ADM1027