LTC1873EG#TR Linear Technology, LTC1873EG#TR Datasheet - Page 10

• Manufacturer Part Number: LTC1873EG#TR
• Description: IC REG SW 2PH DUAL SYNC 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC1873EG#TR

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 750kHz
• Duty Cycle: 93%
• Voltage - Supply: 3 V ~ 7 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Frequency-max: 750kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1873
Switching Architecture
Each half of the LTC1873 is designed to operate as a
synchronous buck converter (Figure 1). Each channel
includes two high power MOSFET gate drivers to control
external N-channel MOSFETs QT and QB. These drivers
have 0.5 output impedances and can carry well over an
amp of continuous current with peak currents up to 5A to
slew large MOSFET gates quickly. The external MOSFETs
are connected with the drain of QT attached to the input
supply and the source of QT at the switching node SW. QB
is the synchronous rectifier with its drain at SW and its
source at PGND. SW is connected to one end of the
inductor, with the other end connected to V
capacitor is connected from V
When a switching cycle begins, QB is turned off and QT is
turned on. SW rises almost immediately to V
inductor current begins to increase. When the PWM pulse
finishes, QT turns off and one nonoverlap interval later, QB
turns on. Now SW drops to PGND and the inductor current
decreases. The cycle repeats with the next tick of the
master clock. The percentage of time spent in each mode
is controlled by the duty cycle of the PWM signal, which in
turn is controlled by the feedback amplifier. The master
clock runs at a 550kHz rate and turns QT once every 1.8 s.
In a typical application with a 5V input and a 1.5V output,
the duty cycle will be set at 1.5/5 100% or 30% by the
feedback loop. This will give roughly a 540ns on-time for
QT and a 1.26 s on-time for QB.
This constant frequency operation brings with it a couple
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feed-
back loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
10
LTC1873
PGND
1/2
Figure 1. Synchronous Buck Architecture
SW
TG
BG
U
V
U
IN
QT
QB
OUT
L
EXT
to PGND.
W
+
+
C
C
OUT
IN
OUT
. The output
1873 F01
V
IN
U
OUT
and the
frequency band with the 550kHz frequency designed to
leave the 455kHz IF band free of interference. Subharmonic
oscillation and slope compensation, common headaches
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1873.
During the time that QT is on, its source (the SW pin) is at
V
ever, QT requires V
minimum R
it needs to generate a gate drive signal at TG higher than
its highest supply voltage. To accomplish this, the TG
driver runs from floating supplies, with its negative supply
attached to SW and its power supply at BOOST. This allows
it to slew up and down with the source of QT. In combination
with a simple external charge pump (Figure 2), this allows
the LTC1873 to completely enhance the gate of QT without
requiring an additional, higher supply voltage.
The two channels of the LTC1873 run from a common
clock, with the phasing chosen to be 180 from side 1 to
side 2. This has the effect of doubling the frequency of the
switching pulses seen by the input bypass capacitor,
significantly lowering the RMS current seen by the capaci-
tor and reducing the value required (see the 2-Phase
section).
Feedback Amplifier
Each side of the LTC1873 senses the output voltage at
V
gram). This is a real op amp with a low impedance output,
85dB open-loop gain and 25MHz gain-bandwidth product.
The positive input is connected internally to an 800mV
reference, while the negative input is connected to the FB
IN
OUT
. V
LTC1873
with an internal feedback op amp (see Block Dia-
IN
is also the power supply for the LTC1873. How-
PV
ON
CC
Figure 2. Floating TG Driver Supply
. This presents a problem for the LTC1873—
PGND
BOOST
SW
TG
BG
IN
+ V
GS(ON)
D
C
1 F
CP
CP
V
at its gate to achieve
IN
QT
QB
L
EXT
+
+
C
C
OUT
IN
V
1873 F02
OUT