ISL6559CRZ-T Intersil, ISL6559CRZ-T Datasheet - Page 5

• Manufacturer Part Number: ISL6559CRZ-T
• Description: IC CTRLR PWM MULTIPHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6559CRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

COMP
RGND
VDIFF
VSEN
IOUT
ISL6559CB (28 LEAD SOIC)
GND
VID4
VID3
VID2
VID1
VID0
OVP
OFS
FB
Electrical Specifications
NOTE:
Functional Pin Description
GND
Bias and reference ground for the IC.
OVP
Over-voltage protection pin. This pin pulls to VCC and is
latched when an over-voltage condition is detected. Connect
ERROR AMPLIFIER
Open-Loop Gain
Open-Loop Bandwidth
Slew Rate
Maximum Output Voltage
Source Current
Sink Current
REMOTE-SENSE AMPLIFIER
Input Impedance
Bandwidth
Slew Rate
SENSE CURRENT
IOUT Accuracy
ISEN Offset Voltage
Over-Current Trip Level
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
Under-Voltage Offset From VID
Over-Voltage Threshold
OVP Voltage
3. These parts are designed and adjusted for accuracy within the system tolerance
10
11
12
13
14
1
2
3
4
5
6
7
8
9
TOP VIEW
PARAMETER
28
27
26
25
24
23
22
21
20
19
18
17
16
15
EN
FS/DIS
PGOOD
PWM4
ISEN4
ISEN1
PWM1
PWM2
GND
ISEN2
ISEN3
PWM3
VCC
GND
COMP
VID2
VID1
VID0
OFS
NC
NC
FB
5
Operating Conditions: VCC = 5V, T
ISL6559CR (32 LEAD QFN)
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
NC = NO CONNECT
TOP VIEW
R
C
C
R
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 50µA
I
VSEN Falling
VSEN Rising
I
PGOOD
OVP
L
L
L
L
= 10kΩ to ground
= 100pF, R
= 100pF, Load = ±400mA
= 10kΩ to ground
= 100mA, VCC = 5V
= 4mA
L
= 10kΩ to ground
24
23
22
21
20
19
18
17
TEST CONDITIONS
PWM4
ISEN4
ISEN1
PWM1
PWM2
GND
ISEN2
ISEN3
ISL6559
A
= 0°C to 70°C. Unless Otherwise Specified. (Continued)
this pin to the gate of an SCR or MOSFET tied across V
and ground to prevent damage to a load device.
VID4, VID3, VID2, VID1, VID0
The state of these five inputs program the internal DAC,
which provides the reference voltage for output regulation.
Connect these pins to either open-drain or active pull-up
type outputs. Pulling these pins above 2.9V can cause a
reference offset inaccuracy.
OFS
Connecting a resistor between this pin and ground creates a
positive offset voltage which is added to the DAC voltage,
allowing easy implementation of load-line regulation. For no
offset, simply tie this pin to ground.
FB and COMP
The internal error amplifier inverting input and output
respectively. Connect the external R-C feedback
compensation network of the regulator to these pins.
IOUT
The current carried out of this pin is proportional to output
current and can be used to incorporate output voltage droop
2.08
MIN
320
3.6
3.0
1.6
2.2
72
-5
-
-
-
-
-
-
-
-
TYP
2.13
3.28
350
7.1
4.5
7.0
3.0
72
18
80
20
90
6
6
-
-
MAX
2.20
108
420
9.5
5.4
0.4
4.0
11
5
-
-
-
-
-
-
-
December 29, 2004
UNITS
FN9084.8
MHz
V/µs
MHz
V/µs
mA
mA
mV
mV
kΩ
dB
µA
%
V
V
V
V
IN