ISL6557ACBZ Intersil, ISL6557ACBZ Datasheet - Page 11

• Manufacturer Part Number: ISL6557ACBZ
• Description: IC CTRLR PWM MULTIPHASE 24-SOIC
• Manufacturer: Intersil

Specifications of ISL6557ACBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 250kHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 250kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

During the soft-start interval, the soft-start voltage, V
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I
decreasing from 160μA down to zero. These signals are
connected as shown in Figure 9 (I
connected to FB depending on the particular application).
The ideal diodes in Figure 9 assure that the controller tries
to regulate its output to the lower of either the reference
voltage or V
across R
not be seen until V
offset. This produces a delay after the ISL6557A enables
before the output voltage starts moving. For example, if
VID = 1.5V, R
can be expressed using Equation 6.
From this point, the soft start ramps linearly until V
reaches VID. For the system described above, this first
linear ramp will continue for approximately
The final portion of the soft-start sequence is the time
remaining after V
zero. This is also characterized by a slight linear ramp in the
output voltage which, for the current example, exists for a time
t
This behavior is seen in the example in Figure 10 of a converter
switching at 500kHz. For this converter, R
t
t
RAMP2
RAMP1
DELAY
R
FB
FIGURE 9. RAMP CURRENT AND VOLTAGE FOR
EXTERNAL CIRCUIT
=
=
=
=
=
R
FB
C
-------------------------------------------------- -
1
5.27ms
T
2.34ms
T
---------- -
1.4
SS
SS
+
RAMP
of R
REGULATING SOFT-START SLOPE
AND DURATION
---------------------------------------- -
R
FB
–
C
–
FB
C
t
1.4 VID
FB
RAMP
t
RAMP1
T
DELAY
= 1kΩ and T
160
. Since I
SS
COMP
VDIFF
RAMP
(
IOUT
times 160μA, the first PWM pulses will
×
FB
reaches VID and before I
10
)
–
–
t
is greater than the R
DELAY
6
RAMP
ISL6557A INTERNAL CIRCUIT
=
11
I
AVG
SS
580μs
creates an initial offset
= 8.3ms, the delay time
OUT
I
RAMP
ERROR AMPLIFIER
may or may not be
V
FB
IDEAL DIODES
RAMP
is set to 2.67kΩ
+
-
FB
RAMP
REFERENCE
VOLTAGE
RAMP
I
V
RAMP
RAMP
COMP
(EQ. 6)
RAMP
(EQ. 7)
(EQ. 8)
gets to
, is
ISL6557A
,
leading to T
and t
NOTE: Switching frequency 500kHz and R
DYNAMIC VID
The ISL6557A is capable of executing on-the-fly output-
voltage changes. At the beginning of the phase-1 switching
cycle (defined in the section entitled PWM Operation), the
ISL6557A checks for a change in the VID code. The VID
code is the bit pattern present at pins VID4-VID0 as outlined
in Voltage Regulation. If the new code remains stable for
another full cycle, the ISL6557A begins incrementing the
reference by making 25mV change every two switching
cycles until the it reaches the new VID code.
Since the ISL6557A recognizes VID-code changes only at
the beginnings of switching cycles, up to one full cycle may
pass before a VID change registers. This is followed by a
one-cycle wait before the output voltage begins to change.
Thus, the total time required for a VID change, t
1.3V
1.3V
FIGURE 10. SOFT-START WAVEFORMS FOR ISL6557A
FIGURE 11. DYNAMIC-VID WAVEFORMS FOR 500KHZ
RAMP2
V
V
01110
REF
OUT
SS
= 1.17ms.
, 100mV/DIV
, 100mV/DIV
BASED MULTI-PHASE BUCK CONVERTER
ISL6557A BASED MULTI-PHASE BUCK
CONVERTER
= 4.0ms, t
t
DELAY
00010
t
RAMP1
DELAY
VID CHANGE OCCURS
ANYWHERE HERE
5μs/DIV
= 700ns, t
t
V
RAMP2
ID
, 5V/DIV
FB
VOUT, 500mV/DIV
EN, 5V/DIV
RAMP1
1ms/DIV
= 2.67kΩ
DV
= 2.23ms,
, is