ISL6308CRZ Intersil, ISL6308CRZ Datasheet - Page 22

• Manufacturer Part Number: ISL6308CRZ
• Description: IC CTRLR PWM 3PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6308CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In Equation 28, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and V
sawtooth signal amplitude as described in “Electrical
Specifications” on page 5.
Once selected, the compensation values in Equation 28
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
value of R
oscilloscope until no further improvement is noted. Normally,
C
Equation 28 unless some performance issue is noted.
The optional capacitor C
noise away from the PWM comparator (see Figure 19). Keep
a position available for C
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Compensating the Converter Operating without
Load-Line Regulation
The ISL6308 multi-phase converter operating without load
line regulation behaves in a similar manner to a voltage
mode controller. This section highlights the design
consideration for a voltage-mode controller requiring external
compensation. To address a broad range of applications, a
type-3 feedback network is recommended (see Figure 20).
Figure 21 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a
small number of adjustments, to the multi-phase ISL6308
circuit. The output voltage (V
voltage, VREF, level. The error amplifier output (COMP pin
voltage) is compared with the oscillator (OSC) modified
Case 3:
1
FIGURE 20. COMPENSATION CONFIGURATION FOR
will not need adjustment. Keep the value of C
C
R
3
2
3
while observing the transient performance on an
NON-LOAD-LINE REGULATED ISL6308 CIRCUIT
F
R
C
0
2
2
>
=
=
R
-------------------------------- -
2π C ESR
R
1
R
-------------------------------------------------------------- -
2π V
2
0.66 V
1
⋅
2
2
⋅
, is sometimes needed to bypass
C
, and be prepared to install a high
⋅
1
2π F
-----------------------------------------------
2
⋅
OUT
0.66 V
OSC
⋅
C
22
1
⋅
IN
) is regulated to the reference
⋅
0
⋅
⋅
R
⋅
ESR
IN
V
1
COMP
VDIFF
OSC
⋅
⋅
FB
F
2
ESR
PP
0
. Slowly increase the
⋅
⋅
⋅
is the peak-to-peak
C
L
L
ISL6308
1
from
ISL6308
sawtooth wave to provide a pulse-width modulated wave with
an amplitude of V
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.
The modulator transfer function is the small-signal transfer
function of V
gain, given by d
filter, with a double pole break frequency at F
F
the individual channel inductance and its DCR divided by 3
(equivalent parallel value of the three output inductors), while
C and ESR represents the total output capacitance and its
equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6308) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45°). Phase margin is the difference
F
CE
LC
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
=
. For the purpose of this analysis, L and DCR represent
CIRCUIT
PWM
---------------------------
2π
⋅
1
COMP
L C
OUT
0
⋅
; typically 0.1 to 0.3 of F
COMPENSATION DESIGN
HALF-BRIDGE
MAX
OSCILLATOR
/V
IN
V
COMP
OSC
E/A
DRIVE
at the PHASE node. The PWM wave is
V
R
IN
ISL6308
2
/V
. This function is dominated by a DC
C
F
+
-
+
VREF
OSC
2
-
CE
C
=
1
, and shaped by the output
-------------------------------- -
2π C ESR
FB
PHASE
UGATE
LGATE
VDIFF
RGND
VSEN
EXTERNAL CIRCUIT
⋅
SW
1
⋅
R
3
V
) and adequate phase
IN
R
1
1
-R
C
LC
L
3
3
, C
September 30, 2008
and a zero at
1
DCR
-C
V
ESR
OUT
C
3
(EQ. 29)
FN9208.4