HIP6521CBZ Intersil, HIP6521CBZ Datasheet - Page 6

• Manufacturer Part Number: HIP6521CBZ
• Description: IC CONTROLLER PWM TRIPLE 16-SOIC
• Manufacturer: Intersil

Specifications of HIP6521CBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 4
• Frequency - Max: 325kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 325kHz
• Input Voltage: 5V
• Output Voltage: 4.5V
• Frequency: 300kHz
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Control Mode: Voltage
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

output voltage. As the internal soft-start voltage increases, the
pulse-width on the PHASE pin increases to reach its
steady-state duty cycle at time T2. At time T3, the 3.3V input
supply starts ramping up; as a result, V
ramping up on the second attempt (approximately 3.25 SS
cycles wait), at time T4. During the interval between T4 and T5,
the linear controller error amplifiers’ references ramp to the final
value bringing all outputs within regulation limits.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s
on-resistance, r
against shorted output. All linear controllers monitor their
respective FB pins for undervoltage events to protect against
excessive currents.
A sustained overload (undervoltage on linears or overcurrent
on the PWM) on any output results in an independent
shutdown of the respective output, followed by subsequent
individual re-start attempts performed at an interval equivalent
to 3 soft-start intervals. Figure 2 describes the protection
feature. At time T0, an overcurrent event sensed across the
switching regulator’s upper MOSFET (r
triggers a shutdown of the V
internal soft-start initiates a number of soft-start cycles. After a
three-cycle wait, the fourth soft-start initiates a ramp-up
attempt of the failed output, at time T2, bringing the output in
regulation at time T4.
To exemplify an UV event on one of the linears, at time T1,
the clock regulator (V
0V
0V
(1V/DIV)
+5V
(0.5V/DIV)
T0
SB
FIGURE 1. SOFT-START INTERVAL
T1
+3.3V
DS(ON)
+5V
DUAL
DUAL
OUT2
to monitor the current for protection
T2
V
) is also subjected to an
OUT1
OUT1
T3
TIME
6
(2.5V)
+3.3V
V
output. As a result, its
OUT3
T4
OUT2
IN
DS(ON)
(1.8V)
and V
sensing)
T5
V
V
OUT4
OUT2
OUT4
(2.5V)
(1.5V)
start
HIP6521
overcurrent event, resulting in an UV condition. Similarly,
after three soft-start periods, the fourth cycle initiates a
ramp-up of this linear output at time T3. One soft-start period
after T3, the linear output is within regulation limits. UV
glitches less than 1µs (typically) in duration are ignored.
As overcurrent protection is performed on the synchronous
switcher regulator on a cycle-by-cycle basis, OC monitoring
is active as long as the regulator is operational. Since the
overcurrent protection on the linear regulators is performed
through undervoltage monitoring at the feedback pins (FB2,
FB3, and FB4), this feature is activated approximately 25%
into the soft-start interval (see Figure 2).
A resistor (R
the PWM converter. As shown in Figure 3, the internal
40µA current sink (I
R
signal enables the overcurrent comparator (OCC). When
the voltage across the upper MOSFET (V
V
overcurrent latch. Both V
to V
V
switching. The overcurrent function will trip at a peak
inductor current (I
The OC trip point varies with MOSFET’s r
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the R
resistor from the equation above with:
I
PEAK
SET
OCSET
0V
OCSET
FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION
IN
(0.5V/DIV.)
UV MONITORING
, the overcurrent comparator trips to set the
and a small capacitor across R
=
T0
I
--------------------------------------------------- -
(V
track the variations of V
OCSET
SET
OCSET
RESPONSE
r
DS ON
) that is referenced to V
T1
×
(
PEAK)
R
OCSET
) programs the overcurrent trip level for
OCSET
)
INACTIVE
determined by:
SET
V
SOFT-START
OUT2
FUNCTION
) develops a voltage across
V
V
TIME
OUT3
OUT4
and V
(2.5V)
(1.8V)
IN
(1.5V)
DS(ON)
due to MOSFET
OCSET
IN
T2
. The DRIVE
DS(ON)
DS(ON)
are referenced
V
helps
OUT1
ACTIVE
OCSET
October 16, 2006
T3
) exceeds
(2.5V)
T4
FN4837.5