ISL6307CRZ Intersil, ISL6307CRZ Datasheet - Page 29

• Manufacturer Part Number: ISL6307CRZ
• Description: IC CTRLR PWM 6-PHASE 48-QFN
• Manufacturer: Intersil

Specifications of ISL6307CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 6
• Frequency - Max: 275kHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-VQFN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

of one or more channels are inhibited from effectively
dissipating their heat so that the affected channels run hotter
than desired, choose new, smaller values of RISEN for the
affected phases (see the section entitled Channel-Current
Balance). Choose R
decrease in temperature rise in order to cause proportionally
less current to flow in the hotter phase.
In Equation 31, make sure that ∆T
rise above the ambient temperature, and ∆T
temperature rise above the ambient temperature. While a
single adjustment according to Equation 31 is usually
sufficient, it may occasionally be necessary to adjust R
two or more times to achieve optimal thermal balance
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labelled R
Its value depends on the desired full-load droop voltage
(V
ISEN resistor, the load-line regulation resistor is as shown in
Equation 32.
If one or more of the ISEN resistors are adjusted for thermal
balance, as in Equation 31, the load-line regulation resistor
should be selected according to Equation 33 where I
full-load operating current and R
connected to the n
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
R
R
R
ISEN 2 ,
FB
FB
DROOP
=
=
V
------------------------ -
--------------------------------
I
50 10
FL
V
=
DROOP
DROOP
×
in Figure 8). If Equation 30 is used to select each
r
R
DS ON
ISEN
–
(
6
∆T
----------
∆T
)
th
∑
ISEN,2
n
2
1
ISEN pin.
R
ISEN n ( )
in proportion to the desired
29
C
and C
ISEN(n)
2
is the desired temperature
C
.
is the ISEN resistor
1
is the measured
FB
in Figure 8.
FL
(EQ. 33)
(EQ. 31)
(EQ. 32)
ISEN
is the
ISL6307
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there are a separate
set of equations for the compensation components
.
In Equation 34, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications.
The optional capacitor C
noise away from the PWM comparator (see Figure 21). Keep
Case 1:
Case 3:
FIGURE 20. COMPENSATION CONFIGURATION FOR
R
FB
LOAD-LINE REGULATED ISL6307 CIRCUIT
f
R
C
-------------------
2π LC
R
C
V
0
+
-
DROOP
C
C
C
C
R
>
1
C
=
=
----------------------------- -
2πC ESR
=
=
C
R
0.75V
------------------------------------------------ -
R
----------------------------------- -
2πV
2
FB
2
2πV
>
FB
, is sometimes needed to bypass
FB
(
C
(OPTIONAL)
1
0.75V
, has already been chosen as
f
C
0
PP
2πf
----------------------------------- -
----------------------------------------- -
0.75 V
PP
IN
0.75V
R
2π f
0
)
R
(
IDROOP
IN
FB
ESR
V
FB
COMP
VDIFF
pp
0
IN
f
0
V
f
IN
0
FB
(
pp
) C
ESR
LC
L
L
PP
0
)
. The target
is the peak-to-
March 9, 2006
FN9224.0
0