ISL6324IRZ Intersil, ISL6324IRZ Datasheet
ISL6324IRZ
Specifications of ISL6324IRZ
Related parts for ISL6324IRZ
ISL6324IRZ Summary of contents
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... MARKING (°C) ISL6324CRZ* ISL6324 CRZ 7x7 QFN L48.7x7 ISL6324IRZ* ISL6324 IRZ - 7x7 QFN L48.7x7 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach ...
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Pinout FB_NB ISEN_NB+ SDA VID0/VFIXEN VID1/SEL VID2/SVD VID3/SVC VID4 VID5 VCC RGND 12 Integrated Driver Block Diagram PWM SOFT-START AND CONTROL FAULT LOGIC 2 ISL6324 ISL6324 ISL6324 HYBRID SVI AND PVI (48 LD QFN) TOP VIEW 48 ...
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Controller Block Diagram SCL CORE_OVP DAC_OFS SDA ISEN_NB+ CURRENT SENSE ISEN_NB- NB_CS VDDPWRGD APA APA COMP VDDPWRGD_MOD FB E/A DVC 2X ∑ RGND PWROK VID0/VFIXEN SVI VID1/SEL SLAVE BUS VID2/SVD DAC_OFS AND VID3/SVC PVI DAC VID4 VID5 ...
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Typical Application - SVI Mode FB VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 VCC BOOT2 UGATE2 FS PHASE2 LGATE2 RSET VFIXEN ISEN2- SEL ISEN2+ SVD SVC RGND VID4 NC VID5 NC PWROK ...
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Typical Application - PVI Mode FB VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 VCC BOOT2 UGATE2 FS PHASE2 LGATE2 RSET VID0 ISEN2- VID1/SEL ISEN2+ VID2 VID3 RGND VID4 VID5 NC PWROK ISEN4+ ...
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... BOOT-PHASE - 0. 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp BOOT + 0.3V BOOT Recommended Operating Conditions VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature ISL6324CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6324IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C TEST CONDITIONS high VCC high PVCC1_2 high PVCC_NB VCC Rising VCC Falling ...
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Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER REFERENCE AND DAC ...
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Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER OVP Lower Gate ...
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Timing Diagram t PDHUGATE UGATE LGATE t FLGATE Functional Pin Description VID1/SEL This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling the ISL6324. If the pin is LO prior to enable, ...
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... MOSFETs’ gates. PWM3 and PWM4 Pulse-width modulation outputs. Connect these pins to the (EQ. 1) PWM input pins of an Intersil driver 4-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to disable them and configure the core VR controller for 2-phase or 3-phase operation. ...
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BOOT_NB This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to appropriately chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC_NB pin provides the necessary bootstrap charge. PHASE_NB Connect this pin ...
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... FS pin and ground. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal has transitioned high ...
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ISL6324 INTERNAL CIRCUIT EXTERNAL CIRCUIT APA - 100µ APA V APA APA,TRIP FILTER COMP AMPLIFIER FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION The APA trip level is the amount of DC offset between the COMP pin and the APA ...
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... SEN current, and making the proper adjustment to each channel , and ISEN pulse width based on the error. Intersil’s patented current balance method is illustrated in Figure 6, with error (EQ. 9) correction for Channel 1 represented. In the figure, the cycle average current, I sample, I ...
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Core and single-phase North Bridge Regulators are disabled and the ISL6324 is continuously sampling voltage on the VID1/SEL pin. When the EN pin is toggled HIGH, the status of the VID1/SEL pin will latch the ISL6324 into ...
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VCC SVC SVD ENABLE PWROK VDD AND VDDNB VDDPWRGD VFIXEN FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP PRE-PWROK METAL VID Typical motherboard start-up occurs with the VFIXEN input low. The controller decodes the SVC ...
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VID values. Details of the SVI Bus protocol are provided in the AMD Design Guide for Voltage Regulator Controllers Accepting Serial VID Codes specification. Once the set VID command is received, the ISL6324 decodes the information to determine ...
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... The integrating compensation network shown in Figure 8 insures that the steady-state error in the output voltage is limited only to the error in the reference voltage, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6324 to include the combined tolerances of each of these elements. The output of the error amplifier, V COMP modulator to generate the PWM signals ...
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VID change, a VID-on-the-fly compensation network is required. This network is composed of a resistor and capacitor in series, R and C DVC DVC and the FB pin DVC R FB VSEN I DVC C ...
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... ICs reach their rising POR level before the ISL6324 becomes enabled. The schematic in Figure 10 demonstrates sequencing the ISL6324 with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. When selecting the value of the resistor divider the driver maximum rising POR threshold should be used for calculating the proper resistor values ...
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V NB 400mV/DIV TDA TDB EN 5V/DIV VDDPWRGD 5V/DIV 100µs/DIV FIGURE 11. SOFT-START WAVEFORMS Pre-Biased Soft-Start The ISL6324 also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. The FB pin is monitored ...
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Overvoltage Protection The ISL6324 constantly monitors the sensed output voltage on the VSEN pin to detect if an overvoltage event occurs. When the output voltage rises above the OVP trip level and exceeds the VDDPWRGD OV limit actions are taken ...
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This will result in a continuous hiccup mode. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. OUTPUT CURRENT, 50A/DIV 0A OUTPUT VOLTAGE, ...
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SDA SCL DATA LINE CHANGE STABLE OF DATA DATA VALID ALLOWED FIGURE 15. DATA VALIDITY START and STOP Conditions Figure 16 shows a START (S) condition is a HIGH to LOW transition of the SDA line while SCL is ...
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ISL6324, it sends the register address byte 0000_0000, representing the internal register RGS1. The ISL6324 will respond with an Acknowledge. After sending the data byte to RGS1 and receiving an Acknowledge from the ISL6324, instead of sending a Stop ...
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Register Bit Definitions The bits for RGS1 and RGS2 are utilized in the same manner by the ISL6324. Bit-7 enables the overvoltage protection trip point to be increased. Bit-6 enables the Power Good trip point to be increased. These bits ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following sections. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials and example board layouts for all common microprocessor applications ...
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Internal Bootstrap Device All three integrated drivers feature an internal bootstrap Schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from ...
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PVCC HI2 LGATE LO2 G2 FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The ...
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So, the R resistor for the Core inductor RC filters is 2 left unpopulated and Choose a capacitor value for the Core RC filter. A 0.1µF capacitor is a recommended starting point. 2. Calculate the ...
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Inductor DCR Current Sensing Component Fine Tuning V IN UGATE(n) MOSFET DRIVER LGATE(n) INDUCTOR R ISL6323 INTERNAL CIRCUIT I n SAMPLE + V ( ISEN I SEN { To Active Core Channels To North Bridge FIGURE ...
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C (OPTIONAL COMP VSEN FIGURE 23. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6324 CIRCUIT Since the system poles and zero are affected by the values of the components that are meant to compensate ...
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C ESR ⋅ ------------------------------------------- - ⋅ ⋅ ESR – ⋅ ⋅ ESR – ------------------------------------------- - ⋅ 0. ---------------------------------------------------------------------------------------------------- ...
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The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV . This places an upper limit on inductance. MAX Equation 54 gives the upper limit on L for the cases ...
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MOSFET turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression. 0.3 0.2 ...
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VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 R APA C APA LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 C C FILTER VCC BOOT2 FS UGATE2 R FS PHASE2 R SET ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 38 ...